From patchwork Thu Aug 14 02:44:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alison Wang X-Patchwork-Id: 379793 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 9C18014008B for ; Thu, 14 Aug 2014 13:36:04 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DEF4C4B5F1; Thu, 14 Aug 2014 05:36:00 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MdPI3U0OwXkT; Thu, 14 Aug 2014 05:36:00 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DF7F7A7400; Thu, 14 Aug 2014 05:34:58 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BDE654B5F1 for ; Thu, 14 Aug 2014 05:34:48 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8Yf3eKdYI4g4 for ; Thu, 14 Aug 2014 05:34:45 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-by2-obe.outbound.protection.outlook.com (mail-by2lp0239.outbound.protection.outlook.com [207.46.163.239]) by theia.denx.de (Postfix) with ESMTPS id 92F624A052 for ; Thu, 14 Aug 2014 05:34:38 +0200 (CEST) Received: from BN3PR0301CA0017.namprd03.prod.outlook.com (25.160.180.155) by BY2PR03MB377.namprd03.prod.outlook.com (10.242.237.12) with Microsoft SMTP Server (TLS) id 15.0.1005.10; Thu, 14 Aug 2014 03:34:34 +0000 Received: from BN1BFFO11FD003.protection.gbl (2a01:111:f400:7c10::1:111) by BN3PR0301CA0017.outlook.office365.com (2a01:111:e400:4000::27) with Microsoft SMTP Server (TLS) id 15.0.1005.10 via Frontend Transport; Thu, 14 Aug 2014 03:34:34 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1BFFO11FD003.mail.protection.outlook.com (10.58.144.66) with Microsoft SMTP Server (TLS) id 15.0.1010.11 via Frontend Transport; Thu, 14 Aug 2014 03:34:33 +0000 Received: from rock.ap.freescale.net (rock.ap.freescale.net [10.193.20.106]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s7E3Y70j001619; Wed, 13 Aug 2014 20:34:31 -0700 From: Alison Wang To: , Date: Thu, 14 Aug 2014 10:44:46 +0800 Message-ID: <1407984294-346-11-git-send-email-b18965@freescale.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1407984294-346-1-git-send-email-b18965@freescale.com> References: <1407984294-346-1-git-send-email-b18965@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(54534003)(189002)(199003)(229853001)(80022001)(104166001)(64706001)(104016003)(47776003)(19580395003)(81342001)(74662001)(26826002)(84676001)(87286001)(74502001)(48376002)(85306004)(77982001)(31966008)(102836001)(21056001)(36756003)(19580405001)(44976005)(83322001)(77156001)(6806004)(99396002)(95666004)(89996001)(33646002)(46102001)(76176999)(92726001)(79102001)(105606002)(575784001)(93916002)(76482001)(20776003)(106466001)(68736004)(62966002)(50986999)(88136002)(92566001)(107046002)(50466002)(87936001)(97736001)(83072002)(50226001)(81542001)(85852003)(4396001)(42262002); DIR:OUT; SFP:; SCL:1; SRVR:BY2PR03MB377; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 03030B9493 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=alison.wang@freescale.com; X-OriginatorOrg: freescale.com Subject: [U-Boot] [PATCH v3 10/18] driver/ddr/fsl: Add support of overriding chip select write leveling X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: York Sun JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose. Signed-off-by: York Sun --- Change log: v3: No change. v2: No change. drivers/ddr/fsl/ctrl_regs.c | 3 +++ drivers/ddr/fsl/interactive.c | 2 ++ include/fsl_ddr_sdram.h | 2 ++ 3 files changed, 7 insertions(+) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 5e0ee77..d9cac22 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -2276,6 +2276,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, if (ip_rev > 0x40400) unq_mrs_en = 1; + if (ip_rev > 0x40700) + ddr->debug[18] = popts->cswl_override; + set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en); set_ddr_sdram_mode(ddr, popts, common_dimm, cas_latency, additive_latency, unq_mrs_en); diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index 7fb4187..6aa16b2 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -511,6 +511,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, CTRL_OPTIONS(wrlvl_override), CTRL_OPTIONS(wrlvl_sample), CTRL_OPTIONS(wrlvl_start), + CTRL_OPTIONS(cswl_override), CTRL_OPTIONS(rcw_override), CTRL_OPTIONS(rcw_1), CTRL_OPTIONS(rcw_2), @@ -801,6 +802,7 @@ static void print_memctl_options(const memctl_options_t *popts) CTRL_OPTIONS(wrlvl_override), CTRL_OPTIONS(wrlvl_sample), CTRL_OPTIONS(wrlvl_start), + CTRL_OPTIONS_HEX(cswl_override), CTRL_OPTIONS(rcw_override), CTRL_OPTIONS(rcw_1), CTRL_OPTIONS(rcw_2), diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index e8a2db9..987119b 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -281,6 +281,7 @@ typedef struct memctl_options_partial_s { #define DDR_DATA_BUS_WIDTH_64 0 #define DDR_DATA_BUS_WIDTH_32 1 #define DDR_DATA_BUS_WIDTH_16 2 +#define DDR_CSWL_CS0 0x04000001 /* * Generalized parameters for memory controller configuration, * might be a little specific to the FSL memory controller @@ -340,6 +341,7 @@ typedef struct memctl_options_s { unsigned int cpo_override; unsigned int write_data_delay; /* DQS adjust */ + unsigned int cswl_override; unsigned int wrlvl_override; unsigned int wrlvl_sample; /* Write leveling */ unsigned int wrlvl_start;