From patchwork Fri Aug 1 22:51:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 375888 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id E3DB01400A3 for ; Sat, 2 Aug 2014 08:51:30 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 152384A049; Sat, 2 Aug 2014 00:51:28 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CA8gxvqQ1VSj; Sat, 2 Aug 2014 00:51:26 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 20A6B4A03B; Sat, 2 Aug 2014 00:51:26 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 67F3A4A036 for ; Sat, 2 Aug 2014 00:51:21 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6V2jMqwxOlKZ for ; Sat, 2 Aug 2014 00:51:18 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-by2-obe.outbound.protection.outlook.com (mail-by2lp0240.outbound.protection.outlook.com [207.46.163.240]) by theia.denx.de (Postfix) with ESMTPS id 94F294A02F for ; Sat, 2 Aug 2014 00:51:12 +0200 (CEST) Received: from BL2PR03MB146.namprd03.prod.outlook.com (10.255.230.18) by BL2PR03MB241.namprd03.prod.outlook.com (10.255.231.15) with Microsoft SMTP Server (TLS) id 15.0.995.14; Fri, 1 Aug 2014 22:51:09 +0000 Received: from BN3PR0301CA0001.namprd03.prod.outlook.com (25.160.180.139) by BL2PR03MB146.namprd03.prod.outlook.com (10.255.230.18) with Microsoft SMTP Server (TLS) id 15.0.995.14; Fri, 1 Aug 2014 22:51:06 +0000 Received: from BY2FFO11FD053.protection.gbl (2a01:111:f400:7c0c::132) by BN3PR0301CA0001.outlook.office365.com (2a01:111:e400:4000::11) with Microsoft SMTP Server (TLS) id 15.0.995.14 via Frontend Transport; Fri, 1 Aug 2014 22:51:06 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BY2FFO11FD053.mail.protection.outlook.com (10.1.15.190) with Microsoft SMTP Server (TLS) id 15.0.990.10 via Frontend Transport; Fri, 1 Aug 2014 22:51:05 +0000 Received: from oslab-l1.am.freescale.net ([10.214.82.103]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s71Mp0Q0022018; Fri, 1 Aug 2014 15:51:04 -0700 From: York Sun To: Date: Fri, 1 Aug 2014 15:51:01 -0700 Message-ID: <1406933461-30945-2-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1406933461-30945-1-git-send-email-yorksun@freescale.com> References: <1406933461-30945-1-git-send-email-yorksun@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(979002)(6009001)(199002)(189002)(6806004)(92566001)(110136001)(48376002)(95666004)(102836001)(64706001)(50466002)(89996001)(19580395003)(93916002)(36756003)(81342001)(77982001)(19580405001)(99396002)(107046002)(84676001)(47776003)(104166001)(2351001)(79102001)(88136002)(87936001)(104016003)(85306004)(20776003)(26826002)(77156001)(83072002)(81542001)(50986999)(74662001)(86362001)(106466001)(69596002)(62966002)(74502001)(21056001)(68736004)(81156004)(80022001)(87286001)(76482001)(83322001)(31966008)(92726001)(97736001)(44976005)(229853001)(85852003)(33646002)(46102001)(105606002)(76176999)(50226001)(4396001)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:; SCL:1; SRVR:BL2PR03MB146; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-Forefront-PRVS: 029097202E Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=yorksun@freescale.com; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-OriginatorOrg: freescale.com Cc: York Sun Subject: [U-Boot] [PATCH 2/2] ARMv8/ls2085a_emu: Enable DP-DDR as standalone memory block X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de DP-DDR is used for DPAA, separated from main memory pool for general use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit). Signed-off-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 3 ++- board/freescale/ls2085a/ddr.c | 36 +++++++++++++++++++++++--- board/freescale/ls2085a/ddr.h | 29 +++++++++++++++++++++ board/freescale/ls2085a/ls2085a.c | 13 +++++++++- include/configs/ls2085a_common.h | 14 +++++++++- include/configs/ls2085a_emu.h | 1 + 6 files changed, 90 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index b17410a..f632c82 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -16,6 +16,7 @@ #define CONFIG_SYS_IMMR 0x01000000 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) +#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) @@ -60,7 +61,7 @@ #ifdef CONFIG_LS2085A #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #else #error SoC not defined diff --git a/board/freescale/ls2085a/ddr.c b/board/freescale/ls2085a/ddr.c index 257bc16..d173707 100644 --- a/board/freescale/ls2085a/ddr.c +++ b/board/freescale/ls2085a/ddr.c @@ -18,7 +18,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; - if (ctrl_num > 3) { + if (ctrl_num > 4) { printf("Not supported controller number %d\n", ctrl_num); return; } @@ -30,9 +30,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; */ if (popts->registered_dimm_en) - pbsp = rdimms[0]; + pbsp = rdimms[ctrl_num]; else - pbsp = udimms[0]; + pbsp = udimms[ctrl_num]; /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr @@ -72,6 +72,12 @@ found: pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); + if (ctrl_num == CONFIG_DP_DDR_CTRL) { + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + } /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed @@ -163,6 +169,10 @@ phys_size_t initdram(int board_type) void dram_init_banksize(void) { +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY + phys_size_t dp_ddr_size; +#endif + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; @@ -172,4 +182,24 @@ void dram_init_banksize(void) } else { gd->bd->bi_dram[0].size = gd->ram_size; } + +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY + /* initialize DP-DDR here */ + puts("DP-DDR: "); + /* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ + dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, + CONFIG_DP_DDR_CTRL, + CONFIG_DP_DDR_NUM_CTRLS, + CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, + NULL, NULL, NULL); + if (dp_ddr_size) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->bd->bi_dram[2].size = dp_ddr_size; + } else { + puts("Not detected"); + } +#endif } diff --git a/board/freescale/ls2085a/ddr.h b/board/freescale/ls2085a/ddr.h index 77f6aaf..9958a68 100644 --- a/board/freescale/ls2085a/ddr.h +++ b/board/freescale/ls2085a/ddr.h @@ -33,6 +33,18 @@ static const struct board_specific_parameters udimm0[] = { {} }; +/* DP-DDR DIMM */ +static const struct board_specific_parameters udimm2[] = { + /* + * memory controller 2 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 2140, 0, 4, 4, 0x0, 0x0}, + {1, 2140, 0, 4, 4, 0x0, 0x0}, + {} +}; + static const struct board_specific_parameters rdimm0[] = { /* * memory controller 0 @@ -45,12 +57,29 @@ static const struct board_specific_parameters rdimm0[] = { {} }; +/* DP-DDR DIMM */ +static const struct board_specific_parameters rdimm2[] = { + /* + * memory controller 2 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {4, 2140, 0, 5, 4, 0x0, 0x0}, + {2, 2140, 0, 5, 4, 0x0, 0x0}, + {1, 2140, 0, 4, 4, 0x0, 0x0}, + {} +}; + static const struct board_specific_parameters *udimms[] = { udimm0, + udimm0, + udimm2, }; static const struct board_specific_parameters *rdimms[] = { rdimm0, + rdimm0, + rdimm2, }; diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c index a18db1d..7842b85 100644 --- a/board/freescale/ls2085a/ls2085a.c +++ b/board/freescale/ls2085a/ls2085a.c @@ -29,9 +29,20 @@ int board_early_init_f(void) return 0; } +void detail_board_ddr_info(void) +{ + puts("\nDDR "); + print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_ddr_info(0); + if (gd->bd->bi_dram[2].size) { + puts("\nDP-DDR "); + print_size(gd->bd->bi_dram[2].size, ""); + print_ddr_info(CONFIG_DP_DDR_CTRL); + } +} + int dram_init(void) { - printf("DRAM: "); gd->ram_size = initdram(0); return 0; diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 2bd5a47..1480b56 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -52,6 +52,18 @@ #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 + +#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS +#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL +/* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ +#define CONFIG_SYS_DP_DDR_BASE_PHY 0 +#define CONFIG_DP_DDR_CTRL 2 +#define CONFIG_DP_DDR_NUM_CTRLS 1 +#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 12000000 /* 12MHz */ @@ -174,7 +186,7 @@ #define CONFIG_SYS_CLK_FREQ 133333333 -#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_NR_DRAM_BANKS 3 #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h index a5cea63..487cd99 100644 --- a/include/configs/ls2085a_emu.h +++ b/include/configs/ls2085a_emu.h @@ -13,6 +13,7 @@ #define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS3 0x53 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */