From patchwork Thu Jul 24 10:42:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Przemyslaw Marczak X-Patchwork-Id: 373365 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id ED996140129 for ; Thu, 24 Jul 2014 20:43:06 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E9936A761F; Thu, 24 Jul 2014 12:43:04 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ThP4P-XpstDQ; Thu, 24 Jul 2014 12:43:04 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C2F9AA747D; Thu, 24 Jul 2014 12:43:00 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A887EA747D for ; Thu, 24 Jul 2014 12:42:55 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kyd9ae-gGF4b for ; Thu, 24 Jul 2014 12:42:52 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout4.w1.samsung.com (mailout4.w1.samsung.com [210.118.77.14]) by theia.denx.de (Postfix) with ESMTPS id 99058A7406 for ; Thu, 24 Jul 2014 12:42:48 +0200 (CEST) Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N97006AWPR06I00@mailout4.w1.samsung.com> for u-boot@lists.denx.de; Thu, 24 Jul 2014 11:42:36 +0100 (BST) X-AuditID: cbfec7f4-b7fac6d000006cfe-ff-53d0e325daed Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id 41.7D.27902.523E0D35; Thu, 24 Jul 2014 11:42:45 +0100 (BST) Received: from AMDC1186.digital.local ([106.116.147.185]) by eusync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0N9700FVPPR5XZ50@eusync2.samsung.com>; Thu, 24 Jul 2014 11:42:45 +0100 (BST) From: Przemyslaw Marczak To: u-boot@lists.denx.de Date: Thu, 24 Jul 2014 12:42:01 +0200 Message-id: <1406198521-2989-1-git-send-email-p.marczak@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <53CFCEFD.5040603@samsung.com> References: <53CFCEFD.5040603@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLJMWRmVeSWpSXmKPExsVy+t/xK7qqjy8EGxw9x2zxaP5jZou1R+6y W+y4fIPF4u3eTnYHFo9F37M8zt7ZwejRt2UVYwBzFJdNSmpOZllqkb5dAlfGjnlzGQta1CoO nrjF0sB4WKaLkZNDQsBE4tj8DiYIW0ziwr31bF2MXBxCAksZJbY2NrJAOH1MEhf33WMBqWIT MJDYc+kMM4gtIiAh8av/KiOIzSwQJ7G9dQZYjbCAocTk4+fB4iwCqhIt27eD1fMKuEi8WHOa EWKbnMTJY5NZQWxOAW2JSauns4HYQgJaEq2LD7FNYORdwMiwilE0tTS5oDgpPddQrzgxt7g0 L10vOT93EyMkSL7sYFx8zOoQowAHoxIPL8PDU8FCrIllxZW5hxglOJiVRHi33b4QLMSbklhZ lVqUH19UmpNafIiRiYNTqoFxzr9VHB4PTTZGbug+ZRDZ1v5z8v9NL/bNNU4pfONdtOhUyaSZ zV72v6c1ylyIfc48ef4t5bv385hWzongMl21wcTjQnz69QOJEvM04j6FHzaS3ti6vOXmjsAr N2Q1DupMsmuaNPfKVOPkwDOL735b893vQ86JuzbiFq0iLrZzP3np8D/nW5DGrMRSnJFoqMVc VJwIAHXJxgvwAQAA Cc: m.szyprowski@samsung.com, Przemyslaw Marczak , drake@endlessm.com Subject: [U-Boot] [PATCH] odroid: set MPLL clock to 880MHz X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch changes MPLL from 800MHz to 880MHz on Odroid. Signed-off-by: Przemyslaw Marczak --- board/samsung/odroid/odroid.c | 60 +++++++++++++++++++++---------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 2c5c107..b6f26ee 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -195,8 +195,8 @@ static void board_clock_init(void) while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) continue; - /* Set MPLL to 800MHz */ - set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); + /* Set MPLL to 880MHz */ + set = SDIV(0) | PDIV(3) | MDIV(110) | FSEL(0) | PLL_ENABLE(1); clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); @@ -220,15 +220,15 @@ static void board_clock_init(void) DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7); /* * For: - * MOUTdmc = 800 MHz - * MOUTdphy = 800 MHz + * MOUTdmc = 880 MHz + * MOUTdphy = 880 MHz * - * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3) - * pclk_acp = aclk_acp / (ratio + 1) = 100 (1) - * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1) - * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1) - * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1) - * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1) + * aclk_acp = MOUTdmc / (ratio + 1) = 220 (3) + * pclk_acp = aclk_acp / (ratio + 1) = 110 (1) + * sclk_dphy = MOUTdphy / (ratio + 1) = 440 (1) + * sclk_dmc = MOUTdmc / (ratio + 1) = 440 (1) + * aclk_dmcd = sclk_dmc / (ratio + 1) = 220 (1) + * aclk_dmcp = aclk_dmcd / (ratio + 1) = 110 (1) */ set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) | DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1); @@ -244,13 +244,13 @@ static void board_clock_init(void) C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127); /* * For: - * MOUTg2d = 800 MHz - * MOUTc2c = 800 Mhz + * MOUTg2d = 880 MHz + * MOUTc2c = 880 Mhz * MOUTpwi = 108 MHz * - * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) - * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) - * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 440 (1) + * sclk_c2c = MOUTc2c / (ratio + 1) = 440 (1) + * aclk_c2c = sclk_c2c / (ratio + 1) = 220 (1) * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) */ set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | @@ -282,9 +282,9 @@ static void board_clock_init(void) clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | UART3_RATIO(15) | UART4_RATIO(15); /* - * For MOUTuart0-4: 800MHz + * For MOUTuart0-4: 880MHz * - * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7) + * SCLK_UARTx = MOUTuartX / (ratio + 1) = 110 (7) */ set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) | UART3_RATIO(7) | UART4_RATIO(7); @@ -298,12 +298,12 @@ static void board_clock_init(void) clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) | MMC1_PRE_RATIO(255); /* - * For MOUTmmc0-3 = 800 MHz (MPLL) + * For MOUTmmc0-3 = 880 MHz (MPLL) * - * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7) - * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1) - * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7) - * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1) + * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 110 (7) + * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 60 (1) + * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 110 (7) + * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 60 (1) */ set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) | MMC1_PRE_RATIO(1); @@ -318,12 +318,12 @@ static void board_clock_init(void) clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) | MMC3_PRE_RATIO(255); /* - * For MOUTmmc0-3 = 800 MHz (MPLL) + * For MOUTmmc0-3 = 880 MHz (MPLL) * - * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7) - * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1) - * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7) - * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1) + * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 110 (7) + * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 60 (1) + * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 110 (7) + * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 60 (1) */ set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) | MMC3_PRE_RATIO(1); @@ -337,10 +337,10 @@ static void board_clock_init(void) /* CLK_DIV_FSYS3 */ clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255); /* - * For MOUTmmc4 = 800 MHz (MPLL) + * For MOUTmmc4 = 880 MHz (MPLL) * - * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7) - * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0) + * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 110 (7) + * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 110 (0) */ set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);