From patchwork Sat Jul 12 13:24:00 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Campbell X-Patchwork-Id: 369322 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 815F11400B9 for ; Sat, 12 Jul 2014 23:25:01 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 16259AB657; Sat, 12 Jul 2014 15:24:57 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MvS-Rgam6OPO; Sat, 12 Jul 2014 15:24:56 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3C64CAB65F; Sat, 12 Jul 2014 15:24:28 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D9693AB649 for ; Sat, 12 Jul 2014 15:24:20 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id X8pk704Iwgkn for ; Sat, 12 Jul 2014 15:24:19 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from benson.vm.bytemark.co.uk (benson.vm.bytemark.co.uk [212.110.190.137]) by theia.denx.de (Postfix) with ESMTPS id 7C5DAAB632 for ; Sat, 12 Jul 2014 15:24:14 +0200 (CEST) Received: from cpc22-cmbg14-2-0-cust482.5-4.cable.virginm.net ([86.6.25.227] helo=celaeno.hellion.org.uk) by benson.vm.bytemark.co.uk with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1X5xHh-0005bb-TC; Sat, 12 Jul 2014 14:24:13 +0100 Received: from dagon.hellion.org.uk ([192.168.1.7]) by celaeno.hellion.org.uk with smtp (Exim 4.80) (envelope-from ) id 1X5xHf-0000LK-Bu; Sat, 12 Jul 2014 14:24:12 +0100 Received: by dagon.hellion.org.uk (sSMTP sendmail emulation); Sat, 12 Jul 2014 14:24:11 +0100 From: Ian Campbell To: u-boot@lists.denx.de, Albert Aribaud Date: Sat, 12 Jul 2014 14:24:00 +0100 Message-Id: <1405171448-27310-3-git-send-email-ijc@hellion.org.uk> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1405171421.11981.51.camel@dagon.hellion.org.uk> References: <1405171421.11981.51.camel@dagon.hellion.org.uk> Cc: Tom Rini , Marc Zyngier Subject: [U-Boot] [PATCH v5 03/11] ARM: non-sec: reset CNTVOFF to zero X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Marc Zyngier Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe timers that are not synchronized, effectively seeing time going backward... Signed-off-by: Marc Zyngier Acked-by: Ian Campbell --- arch/arm/cpu/armv7/nonsec_virt.S | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 12de5c2..b5c946f 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -38,10 +38,10 @@ _secure_monitor: bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits orr r1, r1, #0x31 @ enable NS, AW, FW bits -#ifdef CONFIG_ARMV7_VIRT mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT) +#ifdef CONFIG_ARMV7_VIRT orreq r1, r1, #0x100 @ allow HVC instruction #endif @@ -52,7 +52,14 @@ _secure_monitor: mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR #endif + bne 1f + @ Reset CNTVOFF to 0 before leaving monitor mode + mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 + ands r0, r0, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits + movne r0, #0 + mcrrne p15, 4, r0, r0, c14 @ Reset CNTVOFF to zero +1: movs pc, lr @ return to non-secure SVC _hyp_trap: