From patchwork Mon Jun 23 12:53:21 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 362787 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0591B14008F for ; Mon, 23 Jun 2014 22:54:29 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3A3AC4B8D9; Mon, 23 Jun 2014 14:54:22 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gp0VthUOyiFQ; Mon, 23 Jun 2014 14:54:22 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 56A204B8D6; Mon, 23 Jun 2014 14:54:17 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9F3234B8B9 for ; Mon, 23 Jun 2014 14:54:02 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6kOgLi1Rppqf for ; Mon, 23 Jun 2014 14:53:59 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yk0-f176.google.com (mail-yk0-f176.google.com [209.85.160.176]) by theia.denx.de (Postfix) with ESMTPS id 8002B4B895 for ; Mon, 23 Jun 2014 14:53:54 +0200 (CEST) Received: by mail-yk0-f176.google.com with SMTP id 131so4697428ykp.7 for ; Mon, 23 Jun 2014 05:53:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NwZIwj4rQnu2tBz+apTLJomJDph2Myhg17Px4sMi/cY=; b=ch9uQASU8wlVgWVmHqt0E7lRJScdZ3Xjb9pwk4j1vJLjyo3WtR8aZKTGq2bVgcxjQ7 3gd3KwGsDEDYXwxsCyz1KSeKaPAa9YzC/CvHvszKwm6QYrYOwHw/fPjwiqMwKyN5bops Wo0r0zmCjRio3WJQSKbo607Ma2tMDy20dp8MA34bpzxXvGJaJ976UQ72ky/Ge9RdAHN+ AjH201takRpvLxOhIloE1IxIWelVo6ZKmwMI+g0bNJxQS2wINCIW3ZtKPa9CKsw8Atnd 48mppQeWLLg7hbej/p8pyz7L/90B31mNX6xMIwL/vlPIdr83ONg64+zY6bgKaktyAF28 O8tA== X-Received: by 10.236.67.33 with SMTP id i21mr5213632yhd.131.1403528033649; Mon, 23 Jun 2014 05:53:53 -0700 (PDT) Received: from localhost.localdomain ([189.101.176.19]) by mx.google.com with ESMTPSA id f2sm29750408yhc.41.2014.06.23.05.53.51 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 23 Jun 2014 05:53:52 -0700 (PDT) From: Fabio Estevam To: sbabic@denx.de Date: Mon, 23 Jun 2014 09:53:21 -0300 Message-Id: <1403528002-15451-3-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1403528002-15451-1-git-send-email-festevam@gmail.com> References: <1403528002-15451-1-git-send-email-festevam@gmail.com> Cc: Fabio Estevam , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 3/4] mx6: clock: Do not enable sata and ipu clocks X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Fabio Estevam mx6sx does not have sata nor ipu blocks, so do not handle such clocks. Signed-off-by: Fabio Estevam --- Changes since v2: - None Changes since v1: - None arch/arm/cpu/armv7/mx6/clock.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index d31fbbd..51c964c 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -437,6 +437,7 @@ static int enable_enet_pll(uint32_t en) return 0; } +#ifndef CONFIG_MX6SX static void ungate_sata_clock(void) { struct mxc_ccm_reg *const imx_ccm = @@ -445,6 +446,7 @@ static void ungate_sata_clock(void) /* Enable SATA clock. */ setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); } +#endif static void ungate_pcie_clock(void) { @@ -455,11 +457,13 @@ static void ungate_pcie_clock(void) setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK); } +#ifndef CONFIG_MX6SX int enable_sata_clock(void) { ungate_sata_clock(); return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); } +#endif int enable_pcie_clock(void) { @@ -491,7 +495,9 @@ int enable_pcie_clock(void) clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); /* Party time! Ungate the clock to the PCIe. */ +#ifndef CONFIG_MX6SX ungate_sata_clock(); +#endif ungate_pcie_clock(); return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | @@ -573,6 +579,7 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#ifndef CONFIG_MX6SX void enable_ipu_clock(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -581,6 +588,7 @@ void enable_ipu_clock(void) reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; writel(reg, &mxc_ccm->CCGR3); } +#endif /***************************************************/ U_BOOT_CMD(