diff mbox

[U-Boot] ARM: tegra: Disable VPR

Message ID 1403161120-28645-1-git-send-email-acourbot@nvidia.com
State Superseded
Delegated to: Tom Warren
Headers show

Commit Message

Alexandre Courbot June 19, 2014, 6:58 a.m. UTC 
From: Bryan Wu <pengw@nvidia.com>

On Tegra114 and Tegra124 platforms, certain display-related registers cannot
be accessed unless the VPR registers are programmed.  For bootloader, we
probably don't care about VPR, so we disable it (which counts as programming
it, and allows those display-related registers to be accessed.

This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c
in Chromium OS U-Boot project.

Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Signed-off-by: Bryan Wu <pengw@nvidia.com>
[acourbot: ensure write went through, vpr.c style changes]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Cc: Tom Warren <TWarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Terje Bergstrom <tbergstrom@nvidia.com>
---
 arch/arm/cpu/tegra-common/Makefile   |  1 +
 arch/arm/cpu/tegra-common/ap.c       |  3 +++
 arch/arm/cpu/tegra-common/vpr.c      | 43 ++++++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra/ap.h |  3 +++
 arch/arm/include/asm/arch-tegra/mc.h | 45 ++++++++++++++++++++++++++++++++++++
 5 files changed, 95 insertions(+)
 create mode 100644 arch/arm/cpu/tegra-common/vpr.c
 create mode 100644 arch/arm/include/asm/arch-tegra/mc.h

Comments

Stephen Warren June 19, 2014, 4:08 p.m. UTC | #1 
On 06/19/2014 12:58 AM, Alexandre Courbot wrote:
> From: Bryan Wu <pengw@nvidia.com>
> 
> On Tegra114 and Tegra124 platforms, certain display-related registers cannot
> be accessed unless the VPR registers are programmed.  For bootloader, we
> probably don't care about VPR, so we disable it (which counts as programming
> it, and allows those display-related registers to be accessed.

> diff --git a/arch/arm/cpu/tegra-common/vpr.c b/arch/arm/cpu/tegra-common/vpr.c

> +void config_vpr(void)

> +		/* Turn off VPR */
> +		writel(0x00000000, &mc->mc_video_protect_size_mb);
> +		writel(0x00000001, &mc->mc_video_protect_reg_ctrl);

Can we use a #define rather than "1" there, so we know what the bit
means. Also "0" is as good as "0x00000000" and same for "1".

> diff --git a/arch/arm/include/asm/arch-tegra/mc.h b/arch/arm/include/asm/arch-tegra/mc.h

> +/**
> + * Defines the memory controller registers we need/care about
> + */
> +struct mc_ctlr {
> +	u32 reserved0[4];			/* offset 0x00 - 0x0C */
> +	u32 mc_smmu_config;			/* offset 0x10 */
...

Is this entire layout valid for Tegra20/30 too, and identical for
Tegra114/124? If not, I'd prefer that we:

- Define the structure in arch/arm/include/asm/arch-tegraNNN/mc.h, so
it's obvious that it's not identical on all SoCs (or if the differences
are small, then ifdef the fields in the struct without moving the file
to avoid duplicating the identical parts).

- ifdef out the body of config_vpr() except on SoCs where struct mc_ctrl
is defined.

(actually, ifdefing the body might be useful anyway to remove the code
from builds for older SoCs)
diff mbox

Patch

diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile
index 892556e64451..5c541bef557e 100644
--- a/arch/arm/cpu/tegra-common/Makefile
+++ b/arch/arm/cpu/tegra-common/Makefile
@@ -14,3 +14,4 @@  obj-y += clock.o
 obj-y += lowlevel_init.o
 obj-y += pinmux-common.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
+obj-y += vpr.o
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 91d70da65661..a17dfd1e225e 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -163,4 +163,7 @@  void s_init(void)
 
 	/* init the cache */
 	config_cache();
+
+	/* init vpr */
+	config_vpr();
 }
diff --git a/arch/arm/cpu/tegra-common/vpr.c b/arch/arm/cpu/tegra-common/vpr.c
new file mode 100644
index 000000000000..595744254375
--- /dev/null
+++ b/arch/arm/cpu/tegra-common/vpr.c
@@ -0,0 +1,43 @@ 
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra vpr routines */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/mc.h>
+#include <asm/arch/gp_padctrl.h>
+
+/* Configures VPR.  Right now, all we do is turn it off. */
+void config_vpr(void)
+{
+	struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+
+	/* VPR is only in T114 and T124 */
+	switch (tegra_get_chip()) {
+	case CHIPID_TEGRA114:
+	case CHIPID_TEGRA124:
+		/* Turn off VPR */
+		writel(0x00000000, &mc->mc_video_protect_size_mb);
+		writel(0x00000001, &mc->mc_video_protect_reg_ctrl);
+		/* read back to ensure the write went through */
+		readl(&mc->mc_video_protect_reg_ctrl);
+		break;
+	default:
+		break;
+	}
+}
diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h
index bc5851c1d045..908407aeded0 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -65,3 +65,6 @@  int tegra_get_sku_info(void);
 
 /* Do any chip-specific cache config */
 void config_cache(void);
+
+/* Do chip-specific vpr config */
+void config_vpr(void);
diff --git a/arch/arm/include/asm/arch-tegra/mc.h b/arch/arm/include/asm/arch-tegra/mc.h
new file mode 100644
index 000000000000..2fdcf90d7508
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/mc.h
@@ -0,0 +1,45 @@ 
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA_MC_H_
+#define _TEGRA_MC_H_
+
+/**
+ * Defines the memory controller registers we need/care about
+ */
+struct mc_ctlr {
+	u32 reserved0[4];			/* offset 0x00 - 0x0C */
+	u32 mc_smmu_config;			/* offset 0x10 */
+	u32 mc_smmu_tlb_config;			/* offset 0x14 */
+	u32 mc_smmu_ptc_config;			/* offset 0x18 */
+	u32 mc_smmu_ptb_asid;			/* offset 0x1C */
+	u32 mc_smmu_ptb_data;			/* offset 0x20 */
+	u32 reserved1[3];			/* offset 0x24 - 0x2C */
+	u32 mc_smmu_tlb_flush;			/* offset 0x30 */
+	u32 mc_smmu_ptc_flush;			/* offset 0x34 */
+	u32 reserved2[6];			/* offset 0x38 - 0x4C */
+	u32 mc_emem_cfg;			/* offset 0x50 */
+	u32 mc_emem_adr_cfg;			/* offset 0x54 */
+	u32 mc_emem_adr_cfg_dev0;		/* offset 0x58 */
+	u32 mc_emem_adr_cfg_dev1;		/* offset 0x5C */
+	u32 reserved3[12];			/* offset 0x60 - 0x8C */
+	u32 mc_emem_arb_reserved[28];		/* offset 0x90 - 0xFC */
+	u32 reserved4[338];			/* offset 0x100 - 0x644 */
+	u32 mc_video_protect_bom;		/* offset 0x648 */
+	u32 mc_video_protect_size_mb;		/* offset 0x64c */
+	u32 mc_video_protect_reg_ctrl;		/* offset 0x650 */
+};
+#endif	/* _TEGRA_MC_H_ */