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Tue, 17 Jun 2014 18:08:27 +0900 (KST) X-AuditID: cbfee68e-b7fb96d000004bfc-29-53a0058be29c Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 6D.34.08203.B8500A35; Tue, 17 Jun 2014 18:08:27 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N7B002JF2PP9P10@mmp2.samsung.com>; Tue, 17 Jun 2014 18:08:27 +0900 (KST) From: Ajay Kumar To: u-boot@lists.denx.de, mk7.kang@samsung.com, dh09.lee@samsung.com Date: Tue, 17 Jun 2014 14:36:12 +0530 Message-id: <1402995979-32394-4-git-send-email-ajaykumar.rs@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1402995979-32394-1-git-send-email-ajaykumar.rs@samsung.com> References: <1402995979-32394-1-git-send-email-ajaykumar.rs@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrFLMWRmVeSWpSXmKPExsWyRsSkRrebdUGwwZwlBhYH3h9ksbh+3s6i 40gLo8W3LdsYLX4e+85s8XZvJ7sDm8fshossHgs2lXqcvbOD0aNvyyrGAJYoLpuU1JzMstQi fbsEroxHD3awFnxQqJjdydvAeE6qi5GTQ0LAROLfjq+sELaYxIV769m6GLk4hASWMkqsXtXG ClP04MVqJojEdEaJvg3PGCGcCUwSDfua2ECq2AS0JbZNv8kCYosIuEismdnDCGIzC3hLTGre BGYLC8RJbO1bBDaVRUBVor3jJxOIzSvgIdGw6hF7FyMH0DYFiTmTbEDCnAKeEi3tzewgthBQ yYO1d1lA9koIdLNLbJp9lh1ijoDEt8mHWCB6ZSU2HWCGOFpS4uCKGywTGIUXMDKsYhRNLUgu KE5KLzLSK07MLS7NS9dLzs/dxAgM59P/nvXtYLx5wPoQYzLQuInMUqLJ+cB4yCuJNzQ2M7Iw NTE1NjK3NCNNWEmcd9HDpCAhgfTEktTs1NSC1KL4otKc1OJDjEwcnFINjIWCR5QW6IfFHZxQ XHGCOUO96L796bA9qdzumxyvxKyb/yuoICN467GPDyLeLzTwvPh9+RZX2+dv8izdfZwsqv5Y h/leTUm9Jqm57SSbioIn87y0O9rH5mdd/cR17vTX4vmnPqUYV+q8LJd5/s5/1U6jN84t4hz5 9ycnF2ZJ3r3Goin2L/y+jhJLcUaioRZzUXEiACxsnEB9AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOIsWRmVeSWpSXmKPExsVy+t9jQd1u1gXBBv/nqFsceH+QxeL6eTuL jiMtjBbftmxjtPh57Duzxdu9newObB6zGy6yeCzYVOpx9s4ORo++LasYA1iiGhhtMlITU1KL FFLzkvNTMvPSbZW8g+Od403NDAx1DS0tzJUU8hJzU22VXHwCdN0yc4CWKymUJeaUAoUCEouL lfTtME0IDXHTtYBpjND1DQmC6zEyQAMJaxgzHj3YwVrwQaFididvA+M5qS5GTg4JAROJBy9W M0HYYhIX7q1n62Lk4hASmM4o0bfhGSOEM4FJomFfExtIFZuAtsS26TdZQGwRAReJNTN7GEFs ZgFviUnNm8BsYYE4ia19i1hBbBYBVYn2jp9gG3gFPCQaVj1i72LkANqmIDFnkg1ImFPAU6Kl vZkdxBYCKnmw9i7LBEbeBYwMqxhFUwuSC4qT0nMN9YoTc4tL89L1kvNzNzGCo+WZ1A7GlQ0W hxgFOBiVeHgfys4PFmJNLCuuzD3EKMHBrCTCK/QKKMSbklhZlVqUH19UmpNafIgxGeioicxS osn5wEjOK4k3NDYxNzU2tTSxMDGzJE1YSZz3QKt1oJBAemJJanZqakFqEcwWJg5OqQbG0wam a14mnWTgdH7oUrfmRZFay1V/3Zjyt9Xm3D5pz+xzqza0PWlsk+vvV53lf+Bb7c33aTXLmzm6 FoUv9Nmk0Rtm8UrKLEki4e4GOUHfPYyhGVPq7z+Vmsjt59v9dc2ENIe1x8V8Y6YdYuRlPeNZ sf7DjPi5zZLiM8Inxi6Ps4kPDjn/4KgSS3FGoqEWc1FxIgDXmZm92gIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: sjg@google.com, Ajay Kumar Subject: [U-Boot] [PATCH 03/10] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver. Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL. Signed-off-by: Ajay Kumar Acked-by: Simon Glass Tested-by: Simon Glass Acked-by: Simon Glass Tested-by: Simon Glass --- arch/arm/cpu/armv7/exynos/clock.c | 74 +++++++++++++++++++++++++++++-- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +- arch/arm/include/asm/arch-exynos/clk.h | 1 + 3 files changed, 73 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 400d134..c29b12d 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) * VPLL_CON: MIDV [24:16] * BPLL_CON: MIDV [25:16]: Exynos5 */ - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL || + pllreg == SPLL) mask = 0x3ff; else mask = 0x1ff; @@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg) r = readl(&clk->rpll_con0); k = readl(&clk->rpll_con1); break; + case SPLL: + r = readl(&clk->spll_con0); + break; default: printf("Unsupported PLL (%d)\n", pllreg); return 0; @@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void) return pclk; } +static unsigned long exynos5420_get_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long pclk, sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_DISP10 + * FIMD1_SEL [4] + * 0: SCLK_RPLL + * 1: SCLK_SPLL + */ + sel = readl(&clk->src_disp10); + sel &= (1 << 4); + + if (sel) + sclk = get_pll_clk(SPLL); + else + sclk = get_pll_clk(RPLL); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + ratio = readl(&clk->div_disp10); + ratio = ratio & 0xf; + + pclk = sclk / (ratio + 1); + + return pclk; +} + void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void) clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0); } +void exynos5420_set_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned int cfg; + + /* + * CLK_SRC_DISP10 + * FIMD1_SEL [4] + * 0: SCLK_RPLL + * 1: SCLK_SPLL + */ + cfg = readl(&clk->src_disp10); + cfg &= ~(0x1 << 4); + cfg |= (0 << 4); + writel(cfg, &clk->src_disp10); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + cfg = readl(&clk->div_disp10); + cfg &= ~(0xf << 0); + cfg |= (0 << 0); + writel(cfg, &clk->div_disp10); +} + void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1602,14 +1667,17 @@ unsigned long get_lcd_clk(void) { if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); - else - return exynos5_get_lcd_clk(); + else if (proid_is_exynos5420()) + return exynos5420_get_lcd_clk(); + return exynos5_get_lcd_clk(); } void set_lcd_clk(void) { if (cpu_is_exynos4()) exynos4_set_lcd_clk(); + else if (proid_is_exynos5420()) + exynos5420_set_lcd_clk(); else exynos5_set_lcd_clk(); } diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index db8ea86..5eac9cf 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -779,7 +779,7 @@ #define CLK_SRC_TOP2_VAL 0x11101000 #define CLK_SRC_TOP3_VAL 0x11111111 #define CLK_SRC_TOP4_VAL 0x11110111 -#define CLK_SRC_TOP5_VAL 0x11111100 +#define CLK_SRC_TOP5_VAL 0x11111101 #define CLK_SRC_TOP6_VAL 0x11110111 #define CLK_SRC_TOP7_VAL 0x00022200 diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index ffbc07e..db24dc0 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -15,6 +15,7 @@ #define VPLL 4 #define BPLL 5 #define RPLL 6 +#define SPLL 7 #define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8)) #define MASK_RATIO(x) (0xf << (x << 4))