From patchwork Tue Jun 10 18:44:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Balbi X-Patchwork-Id: 358088 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 469EB140076 for ; Wed, 11 Jun 2014 04:45:43 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 84B524A04C; Tue, 10 Jun 2014 20:45:28 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id i8Wa8cOWjbWa; Tue, 10 Jun 2014 20:45:28 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 179A64B576; Tue, 10 Jun 2014 20:44:53 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9E5464A048 for ; Tue, 10 Jun 2014 20:44:49 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gXd6+Adp4fmq for ; Tue, 10 Jun 2014 20:44:46 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by theia.denx.de (Postfix) with ESMTPS id 4E5DC4A033 for ; Tue, 10 Jun 2014 20:44:40 +0200 (CEST) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s5AIicW1007107 for ; Tue, 10 Jun 2014 13:44:38 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s5AIicY0009466 for ; Tue, 10 Jun 2014 13:44:38 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Tue, 10 Jun 2014 13:44:38 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s5AIibDI007417; Tue, 10 Jun 2014 13:44:38 -0500 From: Felipe Balbi To: Tom Rini Date: Tue, 10 Jun 2014 13:44:16 -0500 Message-ID: <1402425857-11891-5-git-send-email-balbi@ti.com> X-Mailer: git-send-email 2.0.0.rc1 In-Reply-To: <1402425857-11891-1-git-send-email-balbi@ti.com> References: <1402425857-11891-1-git-send-email-balbi@ti.com> MIME-Version: 1.0 Cc: Schuyler Patton , Felipe@theia.denx.de, u-boot@lists.denx.de, Steven Kipisz , "\\\"Franklin Cooper Jr.\\\"" Subject: [U-Boot] [PATCH 4/5] board: ti: am43xx: add AM437x SK PHY Address X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de pass correct PHY Address when running on SK so that we have working ethernet with this board too. Signed-off-by: Felipe Balbi --- board/ti/am43xx/board.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index b184c20..054a452 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -227,16 +227,16 @@ static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { .read_idle_ctrl = 0x00050000, .zq_config = 0x50074be4, .temp_alert_config = 0x0, - .emif_ddr_phy_ctlr_1 = 0x0e084007, + .emif_ddr_phy_ctlr_1 = 0x0e084008, .emif_ddr_ext_phy_ctrl_1 = 0x08020080, - .emif_ddr_ext_phy_ctrl_2 = 0x00700070, - .emif_ddr_ext_phy_ctrl_3 = 0x00700070, - .emif_ddr_ext_phy_ctrl_4 = 0x00700070, - .emif_ddr_ext_phy_ctrl_5 = 0x00700070, + .emif_ddr_ext_phy_ctrl_2 = 0x89, + .emif_ddr_ext_phy_ctrl_3 = 0x90, + .emif_ddr_ext_phy_ctrl_4 = 0x8e, + .emif_ddr_ext_phy_ctrl_5 = 0x8d, .emif_rd_wr_lvl_rmp_win = 0x0, - .emif_rd_wr_lvl_rmp_ctl = 0x0, - .emif_rd_wr_lvl_ctl = 0x0, - .emif_rd_wr_exec_thresh = 0x00000405 + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000000, }; const u32 ext_phy_ctrl_const_base_ddr3[] = { @@ -594,6 +594,11 @@ int board_eth_init(bd_t *bis) writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; cpsw_slaves[0].phy_addr = 16; + } else if (board_is_sk()) { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[0].phy_addr = 4; + cpsw_slaves[1].phy_addr = 5; } else { writel(RGMII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;