From patchwork Thu Jun 5 19:23:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 356578 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 29F44140094 for ; Fri, 6 Jun 2014 05:23:35 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7A25E4B7D8; Thu, 5 Jun 2014 21:23:33 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GiCd7-et-Nv1; Thu, 5 Jun 2014 21:23:33 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D18504B7C5; Thu, 5 Jun 2014 21:23:31 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D552E4B7C5 for ; Thu, 5 Jun 2014 21:23:27 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PU8Ucn47f8BC for ; Thu, 5 Jun 2014 21:23:24 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1blp0188.outbound.protection.outlook.com [207.46.163.188]) by theia.denx.de (Postfix) with ESMTPS id 76EB74B7C4 for ; Thu, 5 Jun 2014 21:23:20 +0200 (CEST) Received: from CH1PR03CA010.namprd03.prod.outlook.com (10.255.156.155) by BL2PR03MB145.namprd03.prod.outlook.com (10.255.230.13) with Microsoft SMTP Server (TLS) id 15.0.954.9; Thu, 5 Jun 2014 19:23:18 +0000 Received: from BL2FFO11FD011.protection.gbl (10.255.156.132) by CH1PR03CA010.outlook.office365.com (10.255.156.155) with Microsoft SMTP Server (TLS) id 15.0.954.9 via Frontend Transport; Thu, 5 Jun 2014 19:23:17 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BL2FFO11FD011.mail.protection.outlook.com (10.173.161.17) with Microsoft SMTP Server (TLS) id 15.0.959.15 via Frontend Transport; Thu, 5 Jun 2014 19:23:17 +0000 Received: from oslab-l1.am.freescale.net ([10.214.84.147]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s55JNCee010743; Thu, 5 Jun 2014 12:23:15 -0700 From: York Sun To: Date: Thu, 5 Jun 2014 12:23:08 -0700 Message-ID: <1401996191-23896-2-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1401996191-23896-1-git-send-email-yorksun@freescale.com> References: <1401996191-23896-1-git-send-email-yorksun@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(54534003)(199002)(189002)(104166001)(88136002)(87936001)(62966002)(77982001)(4396001)(50226001)(89996001)(87286001)(85852003)(81342001)(48376002)(104016001)(50466002)(99396002)(81542001)(102836001)(97736001)(92726001)(74662001)(74502001)(575784001)(93916002)(31966008)(26826002)(76482001)(50986999)(76176999)(84676001)(46102001)(92566001)(21056001)(19580405001)(33646001)(83322001)(47776003)(79102001)(20776003)(44976005)(6806004)(77096999)(83072002)(86362001)(64706001)(68736004)(19580395003)(80022001)(36756003)(77156001); DIR:OUT; SFP:; SCL:1; SRVR:BL2PR03MB145; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BL:0; ACTION:Default; RISK:Low; SCL:0; SPMLVL:NotSpam; PCL:0; RULEID: X-Forefront-PRVS: 0233768B38 Received-SPF: Fail (: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=yorksun@freescale.com; X-OriginatorOrg: freescale.com Cc: u-boot@lists.denx.de, David Feng , York Sun Subject: [U-Boot] [Patch v6 2/5] ARMv8: Adjust MMU setup X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Make MMU function reusable. Platform code can setup its own MMU tables. Signed-off-by: York Sun CC: David Feng --- Change log v6: Modified from v4. Add "dsb sy" before setting MMU registers and add "isb" after. v5: Drop the addition of inline function set_pgtable_section() from v4 It is only used twice and causes confusion. v4: new patch, splitted from v3 2/4 Revise set_pgtable_section() to be reused by platform MMU code Add inline function set_ttbr_tcr_mair() to be used by this and platform mmu code arch/arm/cpu/armv8/cache_v8.c | 50 +++++++++++++++----------------------- arch/arm/include/asm/armv8/mmu.h | 24 ++++++++++++++++++ 2 files changed, 44 insertions(+), 30 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index a96ecda..af3c494 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -12,15 +12,14 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SYS_DCACHE_OFF - -static void set_pgtable_section(u64 section, u64 memory_type) +void set_pgtable_section(u64 *page_table, u64 index, u64 section, + u64 memory_type) { - u64 *page_table = (u64 *)gd->arch.tlb_addr; u64 value; - value = (section << SECTION_SHIFT) | PMD_TYPE_SECT | PMD_SECT_AF; + value = section | PMD_TYPE_SECT | PMD_SECT_AF; value |= PMD_ATTRINDX(memory_type); - page_table[section] = value; + page_table[index] = value; } /* to activate the MMU we need to set up virtual memory */ @@ -28,10 +27,13 @@ static void mmu_setup(void) { int i, j, el; bd_t *bd = gd->bd; + u64 *page_table = (u64 *)gd->arch.tlb_addr; /* Setup an identity-mapping for all spaces */ - for (i = 0; i < (PGTABLE_SIZE >> 3); i++) - set_pgtable_section(i, MT_DEVICE_NGNRNE); + for (i = 0; i < (PGTABLE_SIZE >> 3); i++) { + set_pgtable_section(page_table, i, i << SECTION_SHIFT, + MT_DEVICE_NGNRNE); + } /* Setup an identity-mapping for all RAM space */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { @@ -39,38 +41,26 @@ static void mmu_setup(void) ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size; for (j = start >> SECTION_SHIFT; j < end >> SECTION_SHIFT; j++) { - set_pgtable_section(j, MT_NORMAL); + set_pgtable_section(page_table, j, j << SECTION_SHIFT, + MT_NORMAL); } } /* load TTBR0 */ el = current_el(); if (el == 1) { - asm volatile("msr ttbr0_el1, %0" - : : "r" (gd->arch.tlb_addr) : "memory"); - asm volatile("msr tcr_el1, %0" - : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS) - : "memory"); - asm volatile("msr mair_el1, %0" - : : "r" (MEMORY_ATTRIBUTES) : "memory"); + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, + TCR_FLAGS | TCR_EL1_IPS_BITS, + MEMORY_ATTRIBUTES); } else if (el == 2) { - asm volatile("msr ttbr0_el2, %0" - : : "r" (gd->arch.tlb_addr) : "memory"); - asm volatile("msr tcr_el2, %0" - : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS) - : "memory"); - asm volatile("msr mair_el2, %0" - : : "r" (MEMORY_ATTRIBUTES) : "memory"); + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, + TCR_FLAGS | TCR_EL2_IPS_BITS, + MEMORY_ATTRIBUTES); } else { - asm volatile("msr ttbr0_el3, %0" - : : "r" (gd->arch.tlb_addr) : "memory"); - asm volatile("msr tcr_el3, %0" - : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS) - : "memory"); - asm volatile("msr mair_el3, %0" - : : "r" (MEMORY_ATTRIBUTES) : "memory"); + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, + TCR_FLAGS | TCR_EL3_IPS_BITS, + MEMORY_ATTRIBUTES); } - /* enable the mmu */ set_sctlr(get_sctlr() | CR_M); } diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 1193e76..4b7b67b 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -108,4 +108,28 @@ TCR_IRGN_WBWA | \ TCR_T0SZ(VA_BITS)) +#ifndef __ASSEMBLY__ +void set_pgtable_section(u64 *page_table, u64 index, + u64 section, u64 memory_type); +static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) +{ + asm volatile("dsb sy"); + if (el == 1) { + asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory"); + asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory"); + asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory"); + } else if (el == 2) { + asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory"); + asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory"); + asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory"); + } else if (el == 3) { + asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory"); + asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory"); + asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory"); + } else { + hang(); + } + asm volatile("isb"); +} +#endif #endif /* _ASM_ARMV8_MMU_H_ */