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Tue, 03 Jun 2014 21:40:44 +0900 (KST) X-AuditID: cbfee68e-b7fb96d000004bfc-21-538dc24c126a Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id D6.37.07139.C42CD835; Tue, 03 Jun 2014 21:40:44 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N6L00BHSF5R8X10@mmp1.samsung.com>; Tue, 03 Jun 2014 21:40:44 +0900 (KST) From: Akshay Saraswat To: u-boot@lists.denx.de Date: Tue, 03 Jun 2014 18:07:54 +0530 Message-id: <1401799074-3801-6-git-send-email-akshay.s@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1401799074-3801-1-git-send-email-akshay.s@samsung.com> References: <1401799074-3801-1-git-send-email-akshay.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMLMWRmVeSWpSXmKPExsWyRsSkWtfnUG+wwbJuVYtTfx4zWkx+bWIx 9cE5RotvW7YxWix/vZHd4u3eTnaLf8tmsTuwe8xuuMjisXPWXXaPBZtKPc7e2cHo0bdlFWMA axSXTUpqTmZZapG+XQJXxud5zYwFXQIVzZ+eMDYw7uPtYuTgkBAwkfh5w62LkRPIFJO4cG89 WxcjF4eQwFJGicarf5ghEiYSdw88Z4RILGKUmHj3PRNIQkhgApPEjPmeIDabgI7E9iXf2UFs EQEJiV/9V8EamAVWMkrMeL8VLCEs4CsxrfkQO8hmFgFViWk9wSBhXgFnic1zrzFCHKQgMWeS DUiYU8BFouHPfWaIVc4SK9rXgI2UEFjELvGoezYrSIJFQEDi2+RDLBC9shKbDkDdLClxcMUN lgmMwgsYGVYxiqYWJBcUJ6UXGekVJ+YWl+al6yXn525iBAb46X/P+nYw3jxgfYgxGWjcRGYp 0eR8YITklcQbGpsZWZiamBobmVuakSasJM676GFSkJBAemJJanZqakFqUXxRaU5q8SFGJg5O qQbGpv8mnBfu7QyrcVKSs3ZjU3574d/mdS/T2dKcHioHZW5IrMhvbfDJuFARoBPwavrU1Fln /s1fn5XW99gmg/f/RJ6zTzXvcFxKKOxcsI7lp37m79mK825VfL/5uYXh10r2rpNKm+bJOk6/ fvGKgOuTTcuaatSUJq7MK1KxmKFrzlSpMyVoyhI+JZbijERDLeai4kQAvrB3aIYCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrIIsWRmVeSWpSXmKPExsVy+t9jAV2fQ73BBvt+SFqc+vOY0WLyaxOL qQ/OMVp827KN0WL5643sFm/3drJb/Fs2i92B3WN2w0UWj52z7rJ7LNhU6nH2zg5Gj74tqxgD WKMaGG0yUhNTUosUUvOS81My89JtlbyD453jTc0MDHUNLS3MlRTyEnNTbZVcfAJ03TJzgM5Q UihLzCkFCgUkFhcr6dthmhAa4qZrAdMYoesbEgTXY2SABhLWMGZ8ntfMWNAlUNH86QljA+M+ 3i5GTg4JAROJuweeM0LYYhIX7q1n62Lk4hASWMQoMfHueyaQhJDABCaJGfM9QWw2AR2J7Uu+ s4PYIgISEr/6rzKCNDALrGSUmPF+K1hCWMBXYlrzISCbg4NFQFViWk8wSJhXwFli89xrjCBh CQEFiTmTbEDCnAIuEg1/7jNDrHKWWNG+hnECI+8CRoZVjKKpBckFxUnpuUZ6xYm5xaV56XrJ +bmbGMER9Ex6B+OqBotDjAIcjEo8vAEHeoKFWBPLiitzDzFKcDArifD+W98bLMSbklhZlVqU H19UmpNafIgxGeimicxSosn5wOjOK4k3NDYxNzU2tTSxMDGzJE1YSZz3YKt1oJBAemJJanZq akFqEcwWJg5OqQZGK/+TiaIvc898mTVzVc/V7/PLRZYfrHS9tSW/tIz38PJb4bmLTa/rXmyx mfdGujgvQ0//Ttg97rS5OZ8r2pzvBez8Us+g9affbZroY4eses6QpXkqS8/XXX7ZwHRj0cut qwvFEpLNKhtNeRMkxZz36D/sOXezPFt9wta5rx93HzUwqXfeLFCoxFKckWioxVxUnAgAprX5 3eQCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: u-boot-review@google.com, vbendeb@chromium.org Subject: [U-Boot] [PATCH v2 5/5] Exynos: Split 5250 and 5420 memory bank configuration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Michael Pratt Since snow has a different memory configuration than peach, split the configuration between the 5250 and 5420. Exynos 5420 supports runtime memory configuration detection, and can make the determination between 4 and 7 banks at runtime. Include the bank size with the number of banks for context to make the number of banks meaningful. Signed-off-by: Michael Pratt Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass --- Changes since v1: - New patch. include/configs/exynos5-dt.h | 2 -- include/configs/exynos5250-dt.h | 5 +++++ include/configs/exynos5420.h | 4 ++++ 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index d3ef44c..fd607ee 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -161,8 +161,6 @@ #define CONFIG_RD_LVL -#define CONFIG_NR_DRAM_BANKS 8 -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 10b8942..27aa455 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -65,4 +65,9 @@ #define LCD_YRES 1600 #define LCD_BPP LCD_COLOR16 #endif + +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 8 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + #endif /* __CONFIG_5250_H */ diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h index 2ffe5ee..d2a9556 100644 --- a/include/configs/exynos5420.h +++ b/include/configs/exynos5420.h @@ -45,4 +45,8 @@ */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + #endif /* __CONFIG_EXYNOS5420_H */