From patchwork Tue Jun 3 04:04:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 355154 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3FE0E14007F for ; Tue, 3 Jun 2014 14:06:28 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 078A84B913; Tue, 3 Jun 2014 06:06:22 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0Dt4rrGtOBiC; Tue, 3 Jun 2014 06:06:21 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3392A4B8C7; Tue, 3 Jun 2014 06:05:37 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1BBF34B8C4 for ; Tue, 3 Jun 2014 06:05:29 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id A7eaiwNtI5NU for ; Tue, 3 Jun 2014 06:05:26 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-vc0-f201.google.com (mail-vc0-f201.google.com [209.85.220.201]) by theia.denx.de (Postfix) with ESMTPS id 610734B85A for ; Tue, 3 Jun 2014 06:05:08 +0200 (CEST) Received: by mail-vc0-f201.google.com with SMTP id hq11so442643vcb.2 for ; Mon, 02 Jun 2014 21:05:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vwxqMus6z/6fxbjKSv/XE6Pj6PYiF7O9XTJOaG5/mg8=; b=gd4eJekNSSrGOEXpzRYnwcmWvHKmK3HR1ljHfKjWkwYWyVZ1bN5odfwqgYsr3cW1fx p9BBoxlgZ9Auv5MFjweqOno+fxkmMrPe6ai0I1qzqKMdviFEaWwSNa+/4KsZqabkymXz EEo5gkLDljdjnOAw8VqcqkLv4lMTlEuv7Le5Q9VO1PDBVbGkopREjzu4++15k7vHL3Y6 6gaxZz0fVIpBVXzQoOmvaYGXjEI9z3qsjgduEn5LSxfPcGXDisGVkrpgosMICQUb3fUM rh7ghlxnmcxjnATAryYRvLOoYCGOu+cGEw7/ZgQPwK2TLsDuF5G/igXGpAUuUNcyuhq8 Igvw== X-Gm-Message-State: ALoCoQnAX1LdMZd30nHkwDfW2am2B6GAKMda8FDcUsTJ44ogZroT0LdonOn1guYkF/dPQYpEwJ5V X-Received: by 10.224.26.76 with SMTP id d12mr7341557qac.3.1401768307399; Mon, 02 Jun 2014 21:05:07 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id i65si976180yhg.2.2014.06.02.21.05.07 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Jun 2014 21:05:07 -0700 (PDT) Received: from kaki.bld.corp.google.com (kaki.bld.corp.google.com [172.29.216.32]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id 3AEEF31C433; Mon, 2 Jun 2014 21:05:07 -0700 (PDT) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id E6843220C01; Mon, 2 Jun 2014 22:05:06 -0600 (MDT) From: Simon Glass To: U-Boot Mailing List Date: Mon, 2 Jun 2014 22:04:48 -0600 Message-Id: <1401768297-7198-6-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.9.1.423.g4596e3a In-Reply-To: <1401768297-7198-1-git-send-email-sjg@chromium.org> References: <1401768297-7198-1-git-send-email-sjg@chromium.org> Cc: Tom Rini Subject: [U-Boot] [PATCH v3 05/14] am33xx/omap: Allow cache enable for all Sitara/OMAP X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Enable the cache for all devices, unless CONFIG_SYS_DCACHE_OFF is defined. This speeds up the Beaglebone Black boot considerable. (Tested only on Beaglebone Black with SD card boot) Signed-off-by: Simon Glass --- Changes in v3: None Changes in v2: - Update to cover all omap devices arch/arm/cpu/armv7/am33xx/board.c | 8 ---- arch/arm/cpu/armv7/omap-common/Makefile | 4 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 42 ------------------- arch/arm/cpu/armv7/omap-common/omap-cache.c | 56 ++++++++++++++++++++++++++ arch/arm/cpu/armv7/omap3/board.c | 8 ---- 5 files changed, 60 insertions(+), 58 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap-common/omap-cache.c diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 28c16f8..9ae8c34 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -241,11 +241,3 @@ void s_init(void) sdram_init(); } #endif - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif /* !CONFIG_SYS_DCACHE_OFF */ diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 5f5132f..7695e16 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -22,6 +22,10 @@ obj-y += pipe3-phy.o obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o endif +ifeq ($(CONFIG_SYS_DCACHE_OFF),) +obj-y += omap-cache.o +endif + ifeq ($(CONFIG_OMAP34XX),) obj-y += boot-common.o obj-y += lowlevel_init.o diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index ba97d9e..5f50a19 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -18,13 +18,8 @@ #include #include #include -#include #include -#define ARMV7_DCACHE_WRITEBACK 0xe -#define ARMV7_DOMAIN_CLIENT 1 -#define ARMV7_DOMAIN_MASK (0x3 << 0) - DECLARE_GLOBAL_DATA_PTR; void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) @@ -263,40 +258,3 @@ int print_cpuinfo(void) return 0; } #endif - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} - -void dram_bank_mmu_setup(int bank) -{ - bd_t *bd = gd->bd; - int i; - - u32 start = bd->bi_dram[bank].start >> 20; - u32 size = bd->bi_dram[bank].size >> 20; - u32 end = start + size; - - debug("%s: bank: %d\n", __func__, bank); - for (i = start; i < end; i++) - set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); - -} - -void arm_init_domains(void) -{ - u32 reg; - - reg = get_dacr(); - /* - * Set DOMAIN to client access so that all permissions - * set in pagetables are validated by the mmu. - */ - reg &= ~ARMV7_DOMAIN_MASK; - reg |= ARMV7_DOMAIN_CLIENT; - set_dacr(reg); -} -#endif diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c new file mode 100644 index 0000000..579bebf --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/omap-cache.c @@ -0,0 +1,56 @@ +/* + * + * Common functions for OMAP4/5 based boards + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Author : + * Aneesh V + * Steve Sakoman + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ARMV7_DCACHE_WRITEBACK 0xe +#define ARMV7_DOMAIN_CLIENT 1 +#define ARMV7_DOMAIN_MASK (0x3 << 0) + +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} + +void dram_bank_mmu_setup(int bank) +{ + bd_t *bd = gd->bd; + int i; + + u32 start = bd->bi_dram[bank].start >> 20; + u32 size = bd->bi_dram[bank].size >> 20; + u32 end = start + size; + + debug("%s: bank: %d\n", __func__, bank); + for (i = start; i < end; i++) + set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); +} + +void arm_init_domains(void) +{ + u32 reg; + + reg = get_dacr(); + /* + * Set DOMAIN to client access so that all permissions + * set in pagetables are validated by the mmu. + */ + reg &= ~ARMV7_DOMAIN_MASK; + reg |= ARMV7_DOMAIN_CLIENT; + set_dacr(reg); +} diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 9bb1a1c..e252e7f 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -478,11 +478,3 @@ void omap3_outer_cache_disable(void) omap3_update_aux_cr(0, 0x2); } #endif /* !CONFIG_SYS_L2CACHE_OFF */ - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif /* !CONFIG_SYS_DCACHE_OFF */