From patchwork Mon Jun 2 23:13:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 355104 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 86E9314009C for ; Tue, 3 Jun 2014 09:14:07 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CCB2A4B860; Tue, 3 Jun 2014 01:14:05 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id koVAnq9V9vPq; Tue, 3 Jun 2014 01:14:05 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 783104B7D5; Tue, 3 Jun 2014 01:13:53 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2341B4B7D5 for ; Tue, 3 Jun 2014 01:13:51 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4DUh+SovX8aT for ; Tue, 3 Jun 2014 01:13:47 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f181.google.com (mail-pd0-f181.google.com [209.85.192.181]) by theia.denx.de (Postfix) with ESMTPS id 2234B4A050 for ; Tue, 3 Jun 2014 01:13:40 +0200 (CEST) Received: by mail-pd0-f181.google.com with SMTP id z10so3896988pdj.12 for ; Mon, 02 Jun 2014 16:13:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dCDXxc9irEkoGhfZf1LPIy01voeNVtsTetgI7PV47lM=; b=j2wsmKXwr6F1u/oRQ0E3i3lOrwsnttTw14tzYdYsivUAWvWZJP4an75oIqD20z7B+S exqogdUKEh/oUCq2QFtcLv52SgnFVklKylUgjNdlM9hHgc4nSaas5Hc0/ptbR37BS44t THXU7ZrYdT622MkfiEwDYDtcpugeHhaOUubz1bvh0AcuKSqRqUhv7JVUNcB5bCdj5eFY eRZT9zD5o//jhC4MMNW83JkuqhgAv4BSl+PLo/Zk8js0b0rwPQq6lD6ffSaeUFIvWXhI 9zPmPMIS+voZj06VOiMHYpmy5qpehrl9DHA9LnR1oN5jaNUkEnbUaPE1951ZxIU79wSw dKwQ== X-Gm-Message-State: ALoCoQlT5aFgj5T5SybmDA0WHwMF9lv/sAnEzU4uYquxmsp3wRRLIov/ym2xPnRhlta4AlM6JAHJ X-Received: by 10.68.226.197 with SMTP id ru5mr44607408pbc.77.1401750819057; Mon, 02 Jun 2014 16:13:39 -0700 (PDT) Received: from tharvey-gw.gw (68-189-91-139.static.snlo.ca.charter.com. [68.189.91.139]) by mx.google.com with ESMTPSA id fd5sm12699849pad.12.2014.06.02.16.13.37 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 02 Jun 2014 16:13:38 -0700 (PDT) From: Tim Harvey To: Stefano Babic Date: Mon, 2 Jun 2014 16:13:18 -0700 Message-Id: <1401750807-5975-2-git-send-email-tharvey@gateworks.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1401750807-5975-1-git-send-email-tharvey@gateworks.com> References: <1401750807-5975-1-git-send-email-tharvey@gateworks.com> Cc: Otavio Salvador , Scott Wood , u-boot@lists.denx.de, Tom Rini , Stefan Roese Subject: [U-Boot] [PATCH v4 01/10] spl: nand: add support for mxs nand X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This utilizes existing mxs_nand support layer to provide a method to load an image off nand for SPL. The flash device will be detected in order to support multiple flash devices instead of having layout hard coded at build time. Cc: Stefan Roese Cc: Otavio Salvador Cc: Andy Ng Cc: Eric Nelson Cc: Tapani Utriainen Cc: Tom Rini Cc: Scott Wood Signed-off-by: Tim Harvey --- v4: - removed unnecessary parens from return v3: - removed NAND_NCE and NAND_CTRL_CHANGE unused by mxc_nand.c - return specific error types on errors - remove register keyword - let compiler do optimizations v2: - remove dependence on mtdpart, mtdcore, nand_util, nand_ecc, nand_base and nand_bbt to bring SPL down in size. This reduced codesize by about 32k where now mxs_spl_nand is about 12k total. --- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/mxs_nand_spl.c | 231 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 232 insertions(+) create mode 100644 drivers/mtd/nand/mxs_nand_spl.c diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 4eb354d..bf1312a 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -68,5 +68,6 @@ else # minimal SPL drivers obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o +obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o endif # drivers diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c new file mode 100644 index 0000000..0e7c364 --- /dev/null +++ b/drivers/mtd/nand/mxs_nand_spl.c @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Author: Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include + +static nand_info_t mtd; +static struct nand_chip nand_chip; + +static void mxs_nand_command(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + register struct nand_chip *chip = mtd->priv; + u32 timeo, time_start; + + /* write out the command to the device */ + chip->cmd_ctrl(mtd, command, NAND_CLE); + + /* Serially input address */ + if (column != -1) { + chip->cmd_ctrl(mtd, column, NAND_ALE); + chip->cmd_ctrl(mtd, column >> 8, NAND_ALE); + } + if (page_addr != -1) { + chip->cmd_ctrl(mtd, page_addr, NAND_ALE); + chip->cmd_ctrl(mtd, page_addr >> 8, NAND_ALE); + /* One more address cycle for devices > 128MiB */ + if (chip->chipsize > (128 << 20)) + chip->cmd_ctrl(mtd, page_addr >> 16, NAND_ALE); + } + chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0); + + if (command == NAND_CMD_READ0) { + chip->cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_CLE); + chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0); + } + + /* wait for nand ready */ + ndelay(100); + timeo = (CONFIG_SYS_HZ * 20) / 1000; + time_start = get_timer(0); + while (get_timer(time_start) < timeo) { + if (chip->dev_ready(mtd)) + break; + } +} + +static int mxs_flash_ident(struct mtd_info *mtd) +{ + register struct nand_chip *chip = mtd->priv; + int i; + u8 mfg_id, dev_id; + u8 id_data[8]; + struct nand_onfi_params *p = &chip->onfi_params; + + /* Reset the chip */ + chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + /* Send the command for reading device ID */ + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + + /* Read manufacturer and device IDs */ + mfg_id = chip->read_byte(mtd); + dev_id = chip->read_byte(mtd); + + /* Try again to make sure */ + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + for (i = 0; i < 8; i++) + id_data[i] = chip->read_byte(mtd); + if (id_data[0] != mfg_id || id_data[1] != dev_id) { + printf("second ID read did not match"); + return -1; + } + debug("0x%02x:0x%02x ", mfg_id, dev_id); + + /* read ONFI */ + chip->onfi_version = 0; + chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); + if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || + chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') { + return -2; + } + + /* we have ONFI, probe it */ + chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); + chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); + mtd->name = p->model; + mtd->writesize = le32_to_cpu(p->byte_per_page); + mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize; + mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); + chip->chipsize = le32_to_cpu(p->blocks_per_lun); + chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; + /* Calculate the address shift from the page size */ + chip->page_shift = ffs(mtd->writesize) - 1; + chip->phys_erase_shift = ffs(mtd->erasesize) - 1; + /* Convert chipsize to number of pages per chip -1 */ + chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; + chip->badblockbits = 8; + + debug("erasesize=%d (>>%d)\n", mtd->erasesize, chip->phys_erase_shift); + debug("writesize=%d (>>%d)\n", mtd->writesize, chip->page_shift); + debug("oobsize=%d\n", mtd->oobsize); + debug("chipsize=%lld\n", chip->chipsize); + + return 0; +} + +static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page) +{ + register struct nand_chip *chip = mtd->priv; + int ret; + + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page); + ret = nand_chip.ecc.read_page(mtd, chip, buf, 1, page); + if (ret < 0) { + printf("read_page failed %d\n", ret); + return -1; + } + return 0; +} + +static int is_badblock(struct mtd_info *mtd, loff_t offs, int allowbbt) +{ + register struct nand_chip *chip = mtd->priv; + unsigned int block = offs >> chip->phys_erase_shift; + unsigned int page = offs >> chip->page_shift; + + debug("%s offs=0x%08x block:%d page:%d\n", __func__, (int)offs, block, + page); + chip->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); + memset(chip->oob_poi, 0, mtd->oobsize); + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + + return chip->oob_poi[0] != 0xff; +} + +/* setup mtd and nand structs and init mxs_nand driver */ +static int mxs_nand_init(void) +{ + /* return if already initalized */ + if (nand_chip.numchips) + return 0; + + /* init mxs nand driver */ + board_nand_init(&nand_chip); + mtd.priv = &nand_chip; + /* set mtd functions */ + nand_chip.cmdfunc = mxs_nand_command; + nand_chip.numchips = 1; + + /* identify flash device */ + puts("NAND : "); + if (mxs_flash_ident(&mtd)) { + printf("Failed to identify\n"); + return -1; + } + + /* allocate and initialize buffers */ + nand_chip.buffers = memalign(ARCH_DMA_MINALIGN, + sizeof(*nand_chip.buffers)); + nand_chip.oob_poi = nand_chip.buffers->databuf + mtd.writesize; + /* setup flash layout (does not scan as we override that) */ + mtd.size = nand_chip.chipsize; + nand_chip.scan_bbt(&mtd); + + printf("%llu MiB\n", (mtd.size / (1024 * 1024))); + return 0; +} + +int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) +{ + struct nand_chip *chip; + unsigned int page; + unsigned int nand_page_per_block; + unsigned int sz = 0; + + if (mxs_nand_init()) + return -ENODEV; + chip = mtd.priv; + page = offs >> chip->page_shift; + nand_page_per_block = mtd.erasesize / mtd.writesize; + + debug("%s offset:0x%08x len:%d page:%d\n", __func__, offs, size, page); + + size = roundup(size, mtd.writesize); + while (sz < size) { + if (mxs_read_page_ecc(&mtd, buf, page) < 0) + return -1; + sz += mtd.writesize; + offs += mtd.writesize; + page++; + buf += mtd.writesize; + + /* + * Check if we have crossed a block boundary, and if so + * check for bad block. + */ + if (!(page % nand_page_per_block)) { + /* + * Yes, new block. See if this block is good. If not, + * loop until we find a good block. + */ + while (is_badblock(&mtd, offs, 1)) { + page = page + nand_page_per_block; + /* Check i we've reached the end of flash. */ + if (page >= mtd.size >> chip->page_shift) + return -ENOMEM; + } + } + } + + return 0; +} + +int nand_default_bbt(struct mtd_info *mtd) +{ + return 0; +} + +void nand_init(void) +{ +} + +void nand_deselect(void) +{ +} +