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Thu, 22 May 2014 18:34:35 +0900 (KST) X-AuditID: cbfee68f-b7fef6d000003970-ed-537dc4ab8e98 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 1C.42.08203.BA4CD735; Thu, 22 May 2014 18:34:35 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N5Y00MVRYLIUT30@mmp1.samsung.com>; Thu, 22 May 2014 18:34:35 +0900 (KST) From: Akshay Saraswat To: u-boot@lists.denx.de Date: Thu, 22 May 2014 15:03:16 +0530 Message-id: <1400751196-467-1-git-send-email-akshay.s@samsung.com> X-Mailer: git-send-email 1.7.9.5 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrJLMWRmVeSWpSXmKPExsWyRsSkWnf1kdpgg403bCxO/XnMaHF22UE2 i6kPzjFafNuyjdFi+euN7BZv93ayO7B5zG64yOKxc9Zddo8Fm0o9zt7ZwejRt2UVYwBrFJdN SmpOZllqkb5dAlfG983TGQt2yFd0T+tiamC8J9nFyMEhIWAiMfV5VRcjJ5ApJnHh3nq2LkYu DiGBpYwSs6ceYYNImEisPr2XGSKxiFHiw+elUFUTmCQ+di1jBKliE9CR2L7kOzuILSIgIfGr /yojSBGzwGRGidX7PzCDJIQFPCW2Tp4C1sAioCqxoX0RWJxXwEniwtw2NoiTFCTmTLIB6ZUQ +M0m8eziTVaIegGJb5MPsUDUyEpsOsAMcZ2kxMEVN1gmMAouYGRYxSiaWpBcUJyUXmSsV5yY W1yal66XnJ+7iREYrKf/PevfwXj3gPUhxmSgcROZpUST84HBnlcSb2hsZmRhamJqbGRuaUaa sJI47/2HSUFCAumJJanZqakFqUXxRaU5qcWHGJk4OKUaGDdFzqydN2UF63r+mb25Ku+aYl78 vGhwOoVx8jwvuZmsETbL7/gvvJMlFWfbuOT+aRYfSYt8zaSYzAUmz6YEfT85UbWluGXNmv22 Cz+W3dvVH1t5uj/GJe1kUc2UfuGZ5+QXrHZ6u3kqg7nTJnNfg9VnP/9VfFT5wYG1b7rKXSv9 Ux1HHP6tfKLEUpyRaKjFXFScCAANMG9ObAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrOIsWRmVeSWpSXmKPExsVy+t9jAd3VR2qDDZ6/MrY49ecxo8XZZQfZ LKY+OMdo8W3LNkaL5a83slu83dvJ7sDmMbvhIovHzll32T0WbCr1OHtnB6NH35ZVjAGsUQ2M NhmpiSmpRQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlAJygplCXm lAKFAhKLi5X07TBNCA1x07WAaYzQ9Q0JgusxMkADCWsYM75vns5YsEO+ontaF1MD4z3JLkZO DgkBE4nVp/cyQ9hiEhfurWfrYuTiEBJYxCjx4fNSKGcCk8THrmWMIFVsAjoS25d8ZwexRQQk JH71X2UEKWIWmMwosXr/B7BRwgKeElsnTwFrYBFQldjQvggszivgJHFhbhvQVA6gdQoScybZ TGDkXsDIsIpRNLUguaA4KT3XUK84Mbe4NC9dLzk/dxMjOBqeSe1gXNlgcYhRgINRiYf3xvma YCHWxLLiytxDjBIczEoivEGHa4OFeFMSK6tSi/Lji0pzUosPMSYDLZ/ILCWanA+M1LySeENj E3NTY1NLEwsTM0vShJXEeQ+0WgcKCaQnlqRmp6YWpBbBbGHi4JRqYMyv2hFcnbHzaoSlhWP1 l32Pv0/Yzerk/jYyvUdNnMvG74PMqb9KYfmV+oUdxbcmvuNRWVfnHH/nb5xyn6xTFUvq1vZp dzn55C8v5ayW8DVhvtB3kLvsyvYd53KWcj8vS6ziEkw12M24WWvdszdn329OWqi0vf/PXxM2 puywzVzzNzL9ieCNVGIpzkg01GIuKk4EALIp5/zKAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: u-boot-review@google.com Subject: [U-Boot] [PATCH 3/4] DMC: exynos5420: Gate CLKM to when reading PHY_CON13 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Doug Anderson From experiments it appears that PHY_CON13 is glitchy if we sample it when CLKM is running. If we stop CLKM when sampling it the glitches all go away, so we'll do that. We also check the "is it locked" bits of PHY_CON13 and loop until they show that the value sampled actually represents a locked value. It doesn't appear that the glitching and "is it locked" are related, but it seems wise to wait until the PHY tells us the value is good before we use it. In practice we will not loop more than a couple times (and usually won't loop at all). Signed-off-by: Doug Anderson Signed-off-by: Akshay Saraswat Acked-by: Simon Glass --- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 43 +++++++++++++++++++++++++++---- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 1 + 2 files changed, 39 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 0822323..0654c6a 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -233,6 +233,7 @@ int ddr3_mem_ctrl_init(int reset) struct exynos5420_tzasc *tzasc0, *tzasc1; struct mem_timings *mem; uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1; + uint32_t lock0_info, lock1_info; int chip; int i; @@ -396,7 +397,41 @@ int ddr3_mem_ctrl_init(int reset) */ dmc_config_mrs(mem, &drex0->directcmd); dmc_config_mrs(mem, &drex1->directcmd); - } else { + } + + /* + * Get PHY_CON13 from both phys. Gate CLKM around reading since + * PHY_CON13 is glitchy when CLKM is running. We're paranoid and + * wait until we get a "fine lock", though a coarse lock is probably + * OK (we only use the coarse numbers below). We try to gate the + * clock for as short a time as possible in case SDRAM is somehow + * sensitive. sdelay(10) in the loop is arbitrary to make sure + * there is some time for PHY_CON13 to get updated. In practice + * no delay appears to be needed. + */ + val = readl(&clk->gate_bus_cdrex); + while (true) { + writel(val & ~0x1, &clk->gate_bus_cdrex); + lock0_info = readl(&phy0_ctrl->phy_con13); + writel(val, &clk->gate_bus_cdrex); + + if ((lock0_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED) + break; + + sdelay(10); + } + while (true) { + writel(val & ~0x2, &clk->gate_bus_cdrex); + lock1_info = readl(&phy1_ctrl->phy_con13); + writel(val, &clk->gate_bus_cdrex); + + if ((lock1_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED) + break; + + sdelay(10); + } + + if (!reset) { /* * During Suspend-Resume & S/W-Reset, as soon as PMU releases * pad retention, CKE goes high. This causes memory contents @@ -447,15 +482,13 @@ int ddr3_mem_ctrl_init(int reset) val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); writel(val, &phy1_ctrl->phy_con1); - n_lock_r = readl(&phy0_ctrl->phy_con13); - n_lock_w_phy0 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2; + n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2; n_lock_r = readl(&phy0_ctrl->phy_con12); n_lock_r &= ~CTRL_DLL_ON; n_lock_r |= n_lock_w_phy0; writel(n_lock_r, &phy0_ctrl->phy_con12); - n_lock_r = readl(&phy1_ctrl->phy_con13); - n_lock_w_phy1 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2; + n_lock_w_phy1 = (lock1_info & CTRL_LOCK_COARSE_MASK) >> 2; n_lock_r = readl(&phy1_ctrl->phy_con12); n_lock_r &= ~CTRL_DLL_ON; n_lock_r |= n_lock_w_phy1; diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index b50af2f..1cf9caf 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -284,6 +284,7 @@ #define CTRL_DLL_ON (1 << 5) #define CTRL_FORCE_MASK (0x7F << 8) #define CTRL_LOCK_COARSE_MASK (0x7F << 10) +#define CTRL_FINE_LOCKED 0x7 #define CTRL_OFFSETD_RESET_VAL 0x8 #define CTRL_OFFSETD_VAL 0x7F