From patchwork Thu May 22 09:32:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Saraswat X-Patchwork-Id: 351405 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id EA3CD140083 for ; Thu, 22 May 2014 19:34:22 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1F7C04B6EC; Thu, 22 May 2014 11:34:21 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 18KeCCkAvZPZ; Thu, 22 May 2014 11:34:20 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DC9954B6CE; Thu, 22 May 2014 11:34:16 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E09F44B6CE for ; Thu, 22 May 2014 11:34:12 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 81Qow5Sj6ZAR for ; Thu, 22 May 2014 11:34:09 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) by theia.denx.de (Postfix) with ESMTPS id 0F25A4B6CC for ; Thu, 22 May 2014 11:34:04 +0200 (CEST) Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N5Y004F0YKODM00@mailout2.samsung.com> for u-boot@lists.denx.de; Thu, 22 May 2014 18:34:00 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.122]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 92.73.14704.784CD735; Thu, 22 May 2014 18:34:00 +0900 (KST) X-AuditID: cbfee68f-b7fef6d000003970-46-537dc487b3db Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id A3.22.08203.784CD735; Thu, 22 May 2014 18:33:59 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N5Y0010CYKGH100@mmp1.samsung.com>; Thu, 22 May 2014 18:33:59 +0900 (KST) From: Akshay Saraswat To: u-boot@lists.denx.de Date: Thu, 22 May 2014 15:02:38 +0530 Message-id: <1400751158-400-1-git-send-email-akshay.s@samsung.com> X-Mailer: git-send-email 1.7.9.5 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCLMWRmVeSWpSXmKPExsWyRsSkSrfjSG2wwf7nzBan/jxmtJj64Byj xbct2xgtlr/eyG7xdm8nuwOrx+yGiyweO2fdZfdYsKnU4+ydHYwefVtWMQawRnHZpKTmZJal FunbJXBlfLiznrFgkmLFvluLmBsYz0t3MXJySAiYSOz5PYMNwhaTuHBvPZDNxSEksJRR4sOc 6SwwRU1XZ0ElFjFKNDz+zwjhTGCSONnVDNbOJqAjsX3Jd3YQW0RAQuJX/1VGEJtZIEdiX+sR sEnCAn4S/9b9YAaxWQRUJf5OugQW5xVwknh1dRVQLwfQNgWJOZNsQOZLCHxmk3i29hkjRL2A xLfJh1ggamQlNh1ghjhOUuLgihssExgFFzAyrGIUTS1ILihOSi8y1itOzC0uzUvXS87P3cQI DNHT/57172C8e8D6EGMy0LiJzFKiyfnAEM8riTc0NjOyMDUxNTYytzQjTVhJnPf+w6QgIYH0 xJLU7NTUgtSi+KLSnNTiQ4xMHJxSDYxxu2+Z/ynqtzjcmv2KR+Wt0NYi3ZN3rUtrZYqnN7J+ lzvInFvXnSd079u8rqn5HjyuKqnFk64uORTwVigvfO2W3VYBcgo/Ok3l53FJ1Xnt6hGcdMJi mfqezXknV/Le+h/y/djc3HUsvJ/nmM1UfMXJaMJz2O5f4rQ307TKja81rHRQ6VK8NlGJpTgj 0VCLuag4EQC/rCHBZwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrIIsWRmVeSWpSXmKPExsVy+t9jAd32I7XBBv++Wlqc+vOY0WLqg3OM Ft+2bGO0WP56I7vF272d7A6sHrMbLrJ47Jx1l91jwaZSj7N3djB69G1ZxRjAGtXAaJORmpiS WqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtqq+TiE6DrlpkDtF1JoSwxpxQoFJBY XKykb4dpQmiIm64FTGOErm9IEFyPkQEaSFjDmPHhznrGgkmKFftuLWJuYDwv3cXIySEhYCLR dHUWG4QtJnHh3nogm4tDSGARo0TD4/+MEM4EJomTXc1gVWwCOhLbl3xnB7FFBCQkfvVfZQSx mQVyJPa1HmEBsYUF/CT+rfvBDGKzCKhK/J10CSzOK+Ak8erqKqBeDqBtChJzJtlMYORewMiw ilE0tSC5oDgpPddQrzgxt7g0L10vOT93EyM4Ap5J7WBc2WBxiFGAg1GJh/fG+ZpgIdbEsuLK 3EOMEhzMSiK8QYdrg4V4UxIrq1KL8uOLSnNSiw8xJgMtn8gsJZqcD4zOvJJ4Q2MTc1NjU0sT CxMzS9KElcR5D7RaBwoJpCeWpGanphakFsFsYeLglGpg9PNlfHe76l5OUIh0oVxQ6I2nztnp hatKHmx08TS+tkJnA/+VzZVzP4R8EWRSUpsjU3+maolYwD3eY//aVm5/V9Xp/JmV9ewl2Vf1 KhtVMhItCji3e0XmrEpYGrbtdq/ejCIj3+9dBkd+35Gze93SUP3qZPBHDqO42SdUfH9mr7Of eFRFplNDiaU4I9FQi7moOBEA55pHosQCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: u-boot-review@google.com Subject: [U-Boot] [PATCH 1/4] Exynos5: DMC: Modify the definition of ddr3_mem_ctrl_init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Passing fewer arguments is better and mem_iv_size is never used. Let's keep only one argument and make it cleaner. Signed-off-by: Hatim Ali Signed-off-by: Akshay Saraswat Acked-by: Simon Glass --- arch/arm/cpu/armv7/exynos/dmc_common.c | 5 +---- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 10 ++++++---- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 8 +------- 3 files changed, 8 insertions(+), 15 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c b/arch/arm/cpu/armv7/exynos/dmc_common.c index cca925e..acc9e25 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_common.c +++ b/arch/arm/cpu/armv7/exynos/dmc_common.c @@ -155,14 +155,11 @@ void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd) void mem_ctrl_init(int reset) { struct spl_machine_param *param = spl_get_machine_params(); - struct mem_timings *mem; int ret; - mem = clock_get_mem_timings(); - /* If there are any other memory variant, add their init call below */ if (param->mem_type == DDR_MODE_DDR3) { - ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset); + ret = ddr3_mem_ctrl_init(reset); if (ret) { /* will hang if failed to init memory control */ while (1) diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 487e6f4..a89930b 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -28,18 +28,19 @@ static void reset_phy_ctrl(void) writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl); } -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int reset) +int ddr3_mem_ctrl_init(int reset) { unsigned int val; struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; struct exynos5_dmc *dmc; + struct mem_timings *mem; int i; phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy(); phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy() + DMC_OFFSET); dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl(); + mem = clock_get_mem_timings(); if (reset) reset_phy_ctrl(); @@ -221,8 +222,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, #endif #ifdef CONFIG_EXYNOS5420 -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int reset) +int ddr3_mem_ctrl_init(int reset) { struct exynos5420_clock *clk = (struct exynos5420_clock *)samsung_get_base_clock(); @@ -231,6 +231,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl; struct exynos5420_dmc *drex0, *drex1; struct exynos5420_tzasc *tzasc0, *tzasc1; + struct mem_timings *mem; uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1; int chip; int i; @@ -244,6 +245,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc(); tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc() + DMC_OFFSET); + mem = clock_get_mem_timings(); /* Enable PAUSE for DREX */ setbits_le32(&clk->pause, ENABLE_BIT); diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 53b0ace..b50af2f 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -890,16 +890,10 @@ enum { /* * Memory variant specific initialization code for DDR3 * - * @param mem Memory timings for this memory type. - * @param mem_iv_size Memory interleaving size is a configurable parameter - * which the DMC uses to decide how to split a memory - * chunk into smaller chunks to support concurrent - * accesses; may vary across boards. * @param reset Reset DDR PHY during initialization. * @return 0 if ok, SETUP_ERR_... if there is a problem */ -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int reset); +int ddr3_mem_ctrl_init(int reset); /* Memory variant specific initialization code for LPDDR3 */ void lpddr3_mem_ctrl_init(void);