From patchwork Thu May 8 21:26:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Campbell X-Patchwork-Id: 347255 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 37077140094 for ; Fri, 9 May 2014 07:27:31 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DD3434B668; Thu, 8 May 2014 23:27:12 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OqoaFR4KZwrh; Thu, 8 May 2014 23:27:12 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 442624B669; Thu, 8 May 2014 23:26:58 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7948B4B65F for ; Thu, 8 May 2014 23:26:54 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id COOAoC+uZJrA for ; Thu, 8 May 2014 23:26:52 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from benson.vm.bytemark.co.uk (benson.vm.bytemark.co.uk [212.110.190.137]) by theia.denx.de (Postfix) with ESMTPS id 729564B634 for ; Thu, 8 May 2014 23:26:44 +0200 (CEST) Received: from cpc22-cmbg14-2-0-cust482.5-4.cable.virginm.net ([86.6.25.227] helo=hastur.hellion.org.uk) by benson.vm.bytemark.co.uk with esmtpsa (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1WiVpz-0003bw-HV; Thu, 08 May 2014 22:26:44 +0100 Received: by hastur.hellion.org.uk (sSMTP sendmail emulation); Thu, 08 May 2014 22:26:42 +0100 From: Ian Campbell To: u-boot@lists.denx.de Date: Thu, 8 May 2014 22:26:35 +0100 Message-Id: <1399584395-7832-5-git-send-email-ijc@hellion.org.uk> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1399584366.19277.271.camel@hastur.hellion.org.uk> References: <1399584366.19277.271.camel@hastur.hellion.org.uk> Cc: Alexey Brodkin , Ian Campbell Subject: [U-Boot] [PATCH v3 5/5] net/designware: Make DMA burst length configurable and reduce by default X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The correct value for this setting can vary across SoCs and boards, so make it configurable. Also reduce the default value to 8, which is the same default as used in the Linux driver. Signed-off-by: Ian Campbell Cc: Alexey Brodkin --- v3: Pulled into this series instead of sunxi series. --- drivers/net/designware.c | 2 +- drivers/net/designware.h | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index fa816bf..7186e3b 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -249,7 +249,7 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) rx_descs_init(dev); tx_descs_init(dev); - writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode); + writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, &dma_p->opmode); diff --git a/drivers/net/designware.h b/drivers/net/designware.h index eac5e72..e5b5e20 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -77,18 +77,18 @@ struct eth_dma_regs { #define DW_DMA_BASE_OFFSET (0x1000) +/* Default DMA Burst length */ +#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL +#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8 +#endif + /* Bus mode register definitions */ #define FIXEDBURST (1 << 16) #define PRIORXTX_41 (3 << 14) #define PRIORXTX_31 (2 << 14) #define PRIORXTX_21 (1 << 14) #define PRIORXTX_11 (0 << 14) -#define BURST_1 (1 << 8) -#define BURST_2 (2 << 8) -#define BURST_4 (4 << 8) -#define BURST_8 (8 << 8) -#define BURST_16 (16 << 8) -#define BURST_32 (32 << 8) +#define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8) #define RXHIGHPRIO (1 << 1) #define DMAMAC_SRST (1 << 0)