From patchwork Mon May 5 16:46:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 345785 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CAA0B1402C5 for ; Tue, 6 May 2014 02:47:02 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5CA394B89E; Mon, 5 May 2014 18:47:01 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5of6vRhMdoVQ; Mon, 5 May 2014 18:47:01 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 846C74B8A0; Mon, 5 May 2014 18:46:58 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 76B594B851 for ; Mon, 5 May 2014 18:46:56 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vT6B5v3FrD3W for ; Mon, 5 May 2014 18:46:53 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-bl2-obe.outbound.protection.outlook.com (mail-bl2lp0211.outbound.protection.outlook.com [207.46.163.211]) by theia.denx.de (Postfix) with ESMTPS id 130E14B89E for ; Mon, 5 May 2014 18:46:50 +0200 (CEST) Received: from BY2PR03CA037.namprd03.prod.outlook.com (10.242.234.158) by BY2PR03MB253.namprd03.prod.outlook.com (10.242.37.15) with Microsoft SMTP Server (TLS) id 15.0.934.12; Mon, 5 May 2014 16:46:29 +0000 Received: from BN1AFFO11FD010.protection.gbl (2a01:111:f400:7c10::139) by BY2PR03CA037.outlook.office365.com (2a01:111:e400:2c2c::30) with Microsoft SMTP Server (TLS) id 15.0.934.12 via Frontend Transport; Mon, 5 May 2014 16:46:29 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.1) by BN1AFFO11FD010.mail.protection.outlook.com (10.58.52.70) with Microsoft SMTP Server (TLS) id 15.0.929.8 via Frontend Transport; Mon, 5 May 2014 16:46:28 +0000 Received: from fabio-Latitude-E6410.am.freescale.net ([10.29.244.90]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s45GkMSq022821; Mon, 5 May 2014 09:46:26 -0700 From: Fabio Estevam To: Date: Mon, 5 May 2014 13:46:14 -0300 Message-ID: <1399308374-17245-1-git-send-email-fabio.estevam@freescale.com> X-Mailer: git-send-email 1.8.3.2 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.1; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009001)(6009001)(189002)(199002)(21056001)(6806004)(85852003)(81542001)(92726001)(89996001)(87936001)(44976005)(50466002)(4396001)(81342001)(19580405001)(36756003)(83072002)(83322001)(87286001)(92566001)(77156001)(19580395003)(64706001)(88136002)(47776003)(20776003)(48376002)(86362001)(93916002)(79102001)(50226001)(80022001)(77982001)(50986999)(77096999)(74662001)(33646001)(74502001)(76482001)(31966008)(62966002)(99396002)(46102001)(32563001); DIR:OUT; SFP:1101; SCL:1; SRVR:BY2PR03MB253; H:tx30smr01.am.freescale.net; FPR:; MLV:sfv; PTR:gate-tx3.freescale.com; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 0202D21D2F Received-SPF: Fail (: domain of freescale.com does not designate 192.88.168.1 as permitted sender) receiver=; client-ip=192.88.168.1; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.1) smtp.mailfrom=Fabio.Estevam@freescale.com; X-OriginatorOrg: freescale.com Cc: Fabio Estevam , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2] mx6sabred: Add PFUZE100 PMIC support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de mx6sabresd boards have a PFUZE100 PMIC connected to I2C2 bus. Add support for it Signed-off-by: Fabio Estevam --- Changes since v1: - Init the PMIC inside board_late_init() Stefano, I tried your suggestion of calling the pmic init inside power_init_board(), but pmic dump command fails, so I am calling the pmic init from board_late_init() as done on other boards for now. board/freescale/mx6sabresd/mx6sabresd.c | 84 +++++++++++++++++++++++++++++++++ include/configs/mx6sabresd.h | 14 ++++++ include/power/pfuze100_pmic.h | 4 ++ 3 files changed, 102 insertions(+) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 3e314da..adaa70a 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -23,6 +24,9 @@ #include #include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ @@ -39,6 +43,14 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define I2C_PMIC 1 + +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -129,6 +141,19 @@ iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, + .gp = IMX_GPIO_NR(4, 13) + } +}; + static void setup_spi(void) { imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); @@ -426,6 +451,64 @@ int board_init(void) #ifdef CONFIG_MXC_SPI setup_spi(); #endif + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + return 0; +} + +static int pfuze_init(void) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = pmic_init(I2C_PMIC); + if (ret) + return ret; + + p = pmic_get("PFUZE100_PMIC"); + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Increase VGEN3 from 2.5 to 2.8V */ + pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); + reg &= ~0xf; + reg |= 0xa; + pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); + + /* Increase VGEN5 from 2.8 to 3V */ + pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); + reg &= ~0xf; + reg |= 0xc; + pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); + + /* Set SW1AB stanby volage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PUZE_100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(p, PUZE_100_SW1ABCONF, reg); + + /* Set SW1C standby voltage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); + + /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(p, PFUZE100_SW1CCONF, reg); return 0; } @@ -446,6 +529,7 @@ int board_late_init(void) #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif + pfuze_init(); return 0; } diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 0fa6573..d6b8997 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -25,6 +25,8 @@ #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_BOARD_LATE_INIT + #include "mx6sabre_common.h" #define CONFIG_SYS_FSL_USDHC_NUM 3 @@ -59,4 +61,16 @@ #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + #endif /* __MX6QSABRESD_CONFIG_H */ diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h index 2a9032a..8968678 100644 --- a/include/power/pfuze100_pmic.h +++ b/include/power/pfuze100_pmic.h @@ -15,7 +15,11 @@ enum { PFUZE100_FABID = 0x04, PFUZE100_SW1ABVOL = 0x20, + PFUZE100_SW1ABSTBY = 0x21, + PUZE_100_SW1ABCONF = 0x24, PFUZE100_SW1CVOL = 0x2e, + PFUZE100_SW1CSTBY = 0x2f, + PFUZE100_SW1CCONF = 0x32, PFUZE100_SW2VOL = 0x35, PFUZE100_SW3AVOL = 0x3c, PFUZE100_SW3BVOL = 0x43,