From patchwork Wed Apr 23 05:52:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: dietho@gmx.de X-Patchwork-Id: 341715 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id DD99314008A for ; Wed, 23 Apr 2014 17:28:42 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CFD834B5EC; Wed, 23 Apr 2014 09:28:28 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id c4BujbFDP-st; Wed, 23 Apr 2014 09:28:28 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0645C4B601; Wed, 23 Apr 2014 09:28:10 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 021594B5EC for ; Wed, 23 Apr 2014 07:58:13 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vpjR80hc-AZg for ; Wed, 23 Apr 2014 07:58:09 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mout.gmx.net (mout.gmx.net [212.227.15.19]) by theia.denx.de (Postfix) with ESMTPS id 81E7F4B164 for ; Wed, 23 Apr 2014 07:58:07 +0200 (CEST) Received: from labsvn.graf-syteco.lokal ([46.237.201.142]) by mail.gmx.com (mrgmx102) with ESMTPSA (Nemesis) id 0MRSeC-1WWDLf2fFo-00SeMv; Wed, 23 Apr 2014 07:52:59 +0200 From: dietho@gmx.de To: u-boot@lists.denx.de Date: Wed, 23 Apr 2014 07:52:43 +0200 Message-Id: <1398232365-10877-3-git-send-email-dietho@gmx.de> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1398232365-10877-1-git-send-email-dietho@gmx.de> References: <1398232365-10877-1-git-send-email-dietho@gmx.de> X-Provags-ID: V03:K0:oV5cfc8o1P8cOds8+O7YYW22X0zNODE+C5tiQwI93s7tPxQh5eC V6plHEkBNqvmbU+rwfpZ7/rLUzAAE7uWKsbKm5J3/9gXPBNysOsttIpY7eAB0AgkmpG+UAr Aqcl1f5ZnS6ONpdS1VJ6JC0jV69TR1kEDuLEgRs5QhGBfScbrRB7rhibo6G8LdRm4wxJKx5 BI+V+vBGXDcLsaMLZQDSA== X-Mailman-Approved-At: Wed, 23 Apr 2014 09:28:07 +0200 Subject: [U-Boot] [PATCH 2/4] video: Add support for imx25 lcd controller X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Thomas Diener This patch adds support for the imx25 lcd display controller. Signed-off-by: Thomas Diener Acked-by: Anatolij Gustschin --- drivers/video/Makefile | 1 + drivers/video/imx25lcdc.c | 123 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 drivers/video/imx25lcdc.c diff --git a/drivers/video/Makefile b/drivers/video/Makefile index c527029..945f35d 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o obj-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o +obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o diff --git a/drivers/video/imx25lcdc.c b/drivers/video/imx25lcdc.c new file mode 100644 index 0000000..3b45472 --- /dev/null +++ b/drivers/video/imx25lcdc.c @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2011 + * Matthias Weisser + * + * SPDX-License-Identifier: GPL-2.0+ + * + * imx25lcdc.c - Graphic interface for i.MX25 lcd controller + */ + +#include + +#include +#include +#include +#include +#include "videomodes.h" + +/* + * 4MB (at the end of system RAM) + */ +#define VIDEO_MEM_SIZE 0x400000 + +#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */ + +/* + * Graphic Device + */ +static GraphicDevice imx25fb; + +void *video_hw_init(void) +{ + struct lcdc_regs *lcdc = (struct lcdc_regs *)IMX_LCDC_BASE; + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + GraphicDevice *pGD = &imx25fb; + char *s; + u32 *videomem; + + memset(pGD, 0, sizeof(GraphicDevice)); + + pGD->gdfIndex = GDF_16BIT_565RGB; + pGD->gdfBytesPP = 2; + pGD->memSize = VIDEO_MEM_SIZE; + pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE; + + videomem = (u32 *)pGD->frameAdrs; + + s = getenv("videomode"); + if (s != NULL) { + struct ctfb_res_modes var_mode; + u32 lsr, lpcr, lhcr, lvcr; + unsigned long div; + int bpp; + + /* Disable all clocks of the LCDC */ + writel(readl(&ccm->cgr0) & ~((1<<7) | (1<<24)), &ccm->cgr0); + writel(readl(&ccm->cgr1) & ~(1<<29), &ccm->cgr1); + + bpp = video_get_params(&var_mode, s); + + if (bpp == 0) { + var_mode.xres = 320; + var_mode.yres = 240; + var_mode.pixclock = 154000; + var_mode.left_margin = 68; + var_mode.right_margin = 20; + var_mode.upper_margin = 4; + var_mode.lower_margin = 18; + var_mode.hsync_len = 40; + var_mode.vsync_len = 6; + var_mode.sync = 0; + var_mode.vmode = 0; + } + + /* Fill memory with white */ + memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2); + + imx25fb.winSizeX = var_mode.xres; + imx25fb.winSizeY = var_mode.yres; + + /* LCD base clock is 66.6MHZ. We do calculations in kHz */ + div = 66000 / (1000000000L / var_mode.pixclock); + if (div > 63) + div = 63; + if (0 == div) + div = 1; + + lsr = ((var_mode.xres / 16) << 20) | + var_mode.yres; + lpcr = (1 << 31) | + (1 << 30) | + (5 << 25) | + (1 << 23) | + (1 << 22) | + (1 << 19) | + (1 << 7) | + div; + lhcr = (var_mode.right_margin << 0) | + (var_mode.left_margin << 8) | + (var_mode.hsync_len << 26); + + lvcr = (var_mode.lower_margin << 0) | + (var_mode.upper_margin << 8) | + (var_mode.vsync_len << 26); + + writel((uint32_t)videomem, &lcdc->lssar); + writel(lsr, &lcdc->lsr); + writel(var_mode.xres * 2 / 4, &lcdc->lvpwr); + writel(lpcr, &lcdc->lpcr); + writel(lhcr, &lcdc->lhcr); + writel(lvcr, &lcdc->lvcr); + writel(0x00040060, &lcdc->ldcr); + + writel(0xA90300, &lcdc->lpccr); + + /* Ensable all clocks of the LCDC */ + writel(readl(&ccm->cgr0) | ((1<<7) | (1<<24)), &ccm->cgr0); + writel(readl(&ccm->cgr1) | (1<<29), &ccm->cgr1); + } + + return pGD; +} + +