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Wed, 02 Apr 2014 15:17:41 +0900 (KST) X-AuditID: cbfee690-b7f266d00000287c-06-533bab85ddf5 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id FE.F4.29263.58BAB335; Wed, 02 Apr 2014 15:17:41 +0900 (KST) Received: from localhost.localdomain ([10.252.81.186]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N3E0067R45DZT80@mmp2.samsung.com>; Wed, 02 Apr 2014 15:17:41 +0900 (KST) From: Jaehoon Chung To: u-boot@lists.denx.de Date: Wed, 02 Apr 2014 15:17:25 +0900 Message-id: <1396419451-3377-5-git-send-email-jh80.chung@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1396419451-3377-1-git-send-email-jh80.chung@samsung.com> References: <1396419451-3377-1-git-send-email-jh80.chung@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOLMWRmVeSWpSXmKPExsWyRsSkSLd1tXWwQW+nlsXpT9vYLW78amO1 ePNwM6NFx5EWRotdtyezWLzd28nuwOYx7+dEJo+zd3YwevRtWcUYwBzFZZOSmpNZllqkb5fA lXHz7Q62gkVuFccWH2NuYGyy6GLk5JAQMJE49bCVCcIWk7hwbz1bFyMXh5DAUkaJzgefmGCK lt7dzQqRmM4oMWf6K6iqNiaJh0tmsoNUsQnoSGz/dhysQ0RAQuJX/1VGkCJmgcmMEvN69gF1 cHAIC3hLXDioDVLDIqAqcWb3C0aQMK+Aq8TqXVEgpoSAgsScSTYgFZwCbhL7X7SzgdhCQBXn +nvA1koIdLNL7DqxmAlijIDEt8mHWCB6ZSU2HWCGuFlS4uCKGywTGIUXMDKsYhRNLUguKE5K LzLRK07MLS7NS9dLzs/dxAgM5NP/nk3YwXjvgPUhxmSgcROZpUST84GRkFcSb2hsZmRhamJq bGRuaUaasJI4r9qjpCAhgfTEktTs1NSC1KL4otKc1OJDjEwcnFINjFqPwwSceW9s29Pi/cfh wP90B5mnIm95zr7ZuV+x8uWXK/1uUoaTDzvkOs+ZctJ2560Mox0cUZuC+U88MLJykoxIytaI l58qp+Nann7U7Ne6U60bFPayeFmabNissfygU5x69Cxzs7B0VwahR//ftnRavD7tlLmrYJHc Mr3fr80l63+kT4ybr8RSnJFoqMVcVJwIANYTi7Z6AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrCIsWRmVeSWpSXmKPExsVy+t9jQd3W1dbBBouOK1ic/rSN3eLGrzZW izcPNzNadBxpYbTYdXsyi8XbvZ3sDmwe835OZPI4e2cHo0ffllWMAcxRDYw2GamJKalFCql5 yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5qbZKLj4Bum6ZOUCblRTKEnNKgUIBicXFSvp2 mCaEhrjpWsA0Ruj6hgTB9RgZoIGENYwZN9/uYCtY5FZxbPEx5gbGJosuRk4OCQETiaV3d7NC 2GISF+6tZ+ti5OIQEpjOKDFn+isop41J4uGSmewgVWwCOhLbvx1nArFFBCQkfvVfZQQpYhaY zCgxr2cfUAcHh7CAt8SFg9ogNSwCqhJndr9gBAnzCrhKrN4VBWJKCChIzJlkA1LBKeAmsf9F OxuILQRUca6/h20CI+8CRoZVjKKpBckFxUnpuYZ6xYm5xaV56XrJ+bmbGMFx8kxqB+PKBotD jAIcjEo8vAfOWwULsSaWFVfmHmKU4GBWEuHlnGQdLMSbklhZlVqUH19UmpNafIgxGeimicxS osn5wBjOK4k3NDYxM7I0Mje0MDI2J01YSZz3QKt1oJBAemJJanZqakFqEcwWJg5OqQZGMS0J Nr1ti9S07Bfmr3+g99v2kkv43K/L1Yp3vj/fdKVwzxKWXi6Xk3kep97dupia1LYg3dZuzXov r2/nou6zyt9f9XPvzRMrlON1gvpy7xct+5YcubmTu0fM8FStph9fswxv56RH1TNmWJzqahZw XLF2QVBhy3vTM7ZnLJ6y/VkcsDHvgZ+LEktxRqKhFnNRcSIAjU7cpNcCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: Jaehoon Chung , panto@antoniou-consulting.com Subject: [U-Boot] [PATCHv2 04/10] mmc: exynos_dw_mmc: restore the property into host X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Restore the platdata(property of dt) into host struct. Then data's information is maintained and reused anywhere. Signed-off-by: Jaehoon Chung --- drivers/mmc/exynos_dw_mmc.c | 220 +++++++++++++++++++++++++++---------------- include/dwmmc.h | 2 + 2 files changed, 139 insertions(+), 83 deletions(-) diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index b9d41d4..a2a4d75 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -14,6 +14,7 @@ #include #include #include +#include #define DWMMC_MAX_CH_NUM 4 #define DWMMC_MAX_FREQ 52000000 @@ -45,6 +46,13 @@ unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) & DWMCI_DIVRATIO_MASK) + 1; sclk = get_mmc_clk(host->dev_index); + /* + * Assume to know divider value. + * When clock unit is broken, need to set "host->div" + */ + if (host->div) + sclk /= (host->div + 1); + return sclk / clk_div; } @@ -61,26 +69,17 @@ static void exynos_dwmci_board_init(struct dwmci_host *host) } } -/* - * This function adds the mmc channel to be registered with mmc core. - * index - mmc channel number. - * regbase - register base address of mmc channel specified in 'index'. - * bus_width - operating bus width of mmc channel specified in 'index'. - * clksel - value to be written into CLKSEL register in case of FDT. - * NULL in case od non-FDT. - */ -int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) +static int exynos_dwmci_core_init(struct dwmci_host *host, int index) { - struct dwmci_host *host = NULL; unsigned int div; unsigned long freq, sclk; - host = malloc(sizeof(struct dwmci_host)); - if (!host) { - printf("dwmci_host malloc fail!\n"); - return 1; - } + + if (host->bus_hz) + freq = host->bus_hz; + else + freq = DWMMC_MAX_FREQ; + /* request mmc clock vlaue of 52MHz. */ - freq = 52000000; sclk = get_mmc_clk(index); div = DIV_ROUND_UP(sclk, freq); div -= 1; @@ -88,19 +87,15 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) set_mmc_clk(index, div); host->name = "EXYNOS DWMMC"; - host->ioaddr = (void *)regbase; - host->buswidth = bus_width; #ifdef CONFIG_EXYNOS5420 host->quirks = DWMCI_QUIRK_DISABLE_SMU; #endif host->board_init = exynos_dwmci_board_init; - if (clksel) { - host->clksel_val = clksel; - } else { - if (0 == index) + if (!host->clksel_val) { + if (index == 0) host->clksel_val = DWMMC_MMC0_CLKSEL_VAL; - if (2 == index) + if (index == 2) host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; } @@ -115,80 +110,139 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) return 0; } +/* + * This function adds the mmc channel to be registered with mmc core. + * index - mmc channel number. + * regbase - register base address of mmc channel specified in 'index'. + * bus_width - operating bus width of mmc channel specified in 'index'. + * clksel - value to be written into CLKSEL register in case of FDT. + * NULL in case od non-FDT. + */ +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) +{ + struct dwmci_host *host = NULL; + + host = malloc(sizeof(struct dwmci_host)); + if (!host) { + error("dwmci_host malloc fail!\n"); + return -ENOMEM; + } + + host->ioaddr = (void *)regbase; + host->buswidth = bus_width; + + if (clksel) + host->clksel_val = clksel; + + return exynos_dwmci_core_init(host, index); +} + #ifdef CONFIG_OF_CONTROL -int exynos_dwmmc_init(const void *blob) +struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM]; + +static int do_dwmci_init(struct dwmci_host *host) { - int index, bus_width; - int node_list[DWMMC_MAX_CH_NUM]; - int err = 0, dev_id, flag, count, i, compat_id; - u32 clksel_val, base, timing[3]; + int index, flag = 0, err = 0; -#ifdef CONFIG_EXYNOS4 - compat_id = COMPAT_SAMSUNG_EXYNOS4_DWMMC; -#else - compat_id = COMPAT_SAMSUNG_EXYNOS5_DWMMC; -#endif + index = host->dev_index; - count = fdtdec_find_aliases_for_id(blob, "mmc", - compat_id, node_list, DWMMC_MAX_CH_NUM); + flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; + err = exynos_pinmux_config(host->dev_id, flag); + if (err) { + debug("DWMMC not configure\n"); + return err; + } - for (i = 0; i < count; i++) { - int node = node_list[i]; - struct fdt_gpio_state pwr_gpio; + return exynos_dwmci_core_init(host, index); +} - if (node <= 0) - continue; +static int exynos_dwmci_get_config(const void *blob, int node, + struct dwmci_host *host) +{ + int err = 0; + u32 base, clksel_val, timing[3]; - /* Extract device id for each mmc channel */ - dev_id = pinmux_decode_periph_id(blob, node); + /* Extract device id for each mmc channel */ + host->dev_id = pinmux_decode_periph_id(blob, node); - /* Get the bus width from the device node */ - bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); - if (bus_width <= 0) { - debug("DWMMC: Can't get bus-width\n"); - return -1; - } - if (8 == bus_width) - flag = PINMUX_FLAG_8BIT_MODE; - else - flag = PINMUX_FLAG_NONE; - - fdtdec_decode_gpio(blob, node, "pwr-gpios", &pwr_gpio); - if (fdt_gpio_isvalid(&pwr_gpio)) - gpio_direction_output(pwr_gpio.gpio, 1); - /* config pinmux for each mmc channel */ - err = exynos_pinmux_config(dev_id, flag); - if (err) { - debug("DWMMC not configured\n"); - return err; - } + /* Get the bus width from the device node */ + host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0); + if (host->buswidth <= 0) { + debug("DWMMC: Can't get bus-width\n"); + return -EINVAL; + } - index = fdtdec_get_int(blob, node, "index", dev_id); - if (index == dev_id) - index = dev_id - PERIPH_ID_SDMMC0; + host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id); + if (host->dev_index == host->dev_id) + host->dev_index = host->dev_id - PERIPH_ID_SDMMC0; - /* Get the base address from the device node */ - base = fdtdec_get_addr(blob, node, "reg"); - if (!base) { - debug("DWMMC: Can't get base address\n"); - return -1; - } - /* Extract the timing info from the node */ - err = fdtdec_get_int_array(blob, node, "samsung,timing", - timing, 3); + /* Set the base address from the device node */ + base = fdtdec_get_addr(blob, node, "reg"); + if (!base) { + debug("DWMMC: Can't get base address\n"); + return -EINVAL; + } + host->ioaddr = (void *)base; + + /* Extract the timing info from the node */ + err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3); + if (err) { + debug("Can't get sdr-timings for devider\n"); + return -EINVAL; + } + + clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) | + DWMCI_SET_DRV_CLK(timing[1]) | + DWMCI_SET_DIV_RATIO(timing[2])); + if (clksel_val) + host->clksel_val = clksel_val; + + host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0); + host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0); + host->div = fdtdec_get_int(blob, node, "div", 0); + + return 0; +} + +static int exynos_dwmci_process_node(const void *blob, + int node_list[], int count) +{ + struct dwmci_host *host; + int i, node, err; + + for (i = 0; i < count; i++) { + node = node_list[i]; + if (node <= 0) + continue; + host = &dwmci_host[i]; + err = exynos_dwmci_get_config(blob, node, host); if (err) { - debug("Can't get sdr-timings for divider\n"); - return -1; + debug("%s: failed to decode dev %d\n", __func__, i); + return err; } - clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) | - DWMCI_SET_DRV_CLK(timing[1]) | - DWMCI_SET_DIV_RATIO(timing[2])); - /* Initialise each mmc channel */ - err = exynos_dwmci_add_port(index, base, bus_width, clksel_val); - if (err) - debug("dwmmc Channel-%d init failed\n", index); + do_dwmci_init(host); } return 0; } + +int exynos_dwmmc_init(const void *blob) +{ + int compat_id; + int node_list[DWMMC_MAX_CH_NUM]; + int err = 0, count; + + if (cpu_is_exynos4()) + compat_id = COMPAT_SAMSUNG_EXYNOS4_DWMMC; + else if (cpu_is_exynos5()) + compat_id = COMPAT_SAMSUNG_EXYNOS5_DWMMC; + else + compat_id = COMPAT_UNKNOWN; + + count = fdtdec_find_aliases_for_id(blob, "mmc", + compat_id, node_list, DWMMC_MAX_CH_NUM); + err = exynos_dwmci_process_node(blob, node_list, count); + + return err; +} #endif diff --git a/include/dwmmc.h b/include/dwmmc.h index b641558..f391b63 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -134,7 +134,9 @@ struct dwmci_host { unsigned int version; unsigned int clock; unsigned int bus_hz; + unsigned int div; int dev_index; + int dev_id; int buswidth; u32 clksel_val; u32 fifoth_val;