diff --git a/arch/arm/cpu/faraday/a369/Makefile b/arch/arm/cpu/faraday/a369/Makefile
new file mode 100644
index 0000000..8a7c979
--- /dev/null
+++ b/arch/arm/cpu/faraday/a369/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y := ../ftpwmtmr010.o
diff --git a/arch/arm/include/asm/arch-a369/hardware.h b/arch/arm/include/asm/arch-a369/hardware.h
new file mode 100644
index 0000000..9c824ad
--- /dev/null
+++ b/arch/arm/include/asm/arch-a369/hardware.h
@@ -0,0 +1,88 @@
+/*
+ * arch/arm/include/asm/arch-a369/hardware.h
+ *
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_DRAM_BASE            0x10000000
+
+#define CONFIG_SRAM_BASE            0xA0000000
+#define CONFIG_SRAM_SIZE            0x00008000
+
+#define CONFIG_SYSC_BASE            0x92000000
+#define CONFIG_DDRC_BASE            0x93100000
+#define CONFIG_AHBC_BASE            0x94000000
+#define CONFIG_SMC_BASE             0x94800000
+#define CONFIG_AHBC2_BASE           0x94200000
+
+/*
+ * Timer
+ */
+#define CONFIG_FTPWMTMR010_BASE     0x92300000
+#define CONFIG_FTPWMTMR010_IRQ      8
+
+/*
+ * UART
+ */
+#define CONFIG_FTUART010_BASE       0x92B00000
+
+/*
+ * Interrupt
+ */
+#define CONFIG_FTINTC020_BASE0      0x90100000
+#define CONFIG_FTINTC020_BASE1      0x96000000
+#define CONFIG_FTINTC020_BASE       CONFIG_FTINTC020_BASE0
+
+/*
+ * I2C
+ */
+#define CONFIG_FTI2C010_BASE0       0x92900000
+#define CONFIG_FTI2C010_BASE1       0x92A00000
+#define CONFIG_FTI2C010_BASE        CONFIG_FTI2C010_BASE0
+
+/*
+ * WatchDog
+ */
+#define CONFIG_FTWDT010_BASE        0x92200000
+
+/*
+ * NIC
+ */
+#define CONFIG_FTGMAC100_BASE       0x90C00000
+
+/*
+ * SPI
+ */
+#define CONFIG_FTSSP010_BASE        0x92700000
+
+/*
+ * NAND
+ */
+#define CONFIG_FTNANDC021_BASE      0x90200000
+
+/*
+ * LCD
+ */
+#define CONFIG_FTLCDC200_BASE       0x94A00000
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_FTSDC010_BASE        0x90600000
+
+/*
+ * USB
+ */
+#define CONFIG_FUSBH200_BASE        0x90800000    /* FUSBH200 */
+#define CONFIG_FOTG210_BASE         0x90900000    /* FOTG210 */
+
+#endif
diff --git a/arch/arm/include/asm/arch-a369/sysc.h b/arch/arm/include/asm/arch-a369/sysc.h
new file mode 100644
index 0000000..ddf3e70
--- /dev/null
+++ b/arch/arm/include/asm/arch-a369/sysc.h
@@ -0,0 +1,211 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_A369_SYSC_H
+#define _ASM_ARCH_A369_SYSC_H
+
+struct sysc_regs {
+	/* 0x000 ~ 0x0ff */
+	uint32_t idr;      /* ID Register */
+	uint32_t revr;     /* SCU revision id */
+	uint32_t hwcfg;    /* HW configuration strap */
+	uint32_t cpumcfr;  /* CPUM (master) freq. control */
+	uint32_t cr;       /* SCU control register */
+	uint32_t sr;       /* SCU status register */
+	uint32_t rsvd0[1];
+	uint32_t osccr;    /* OSC control register */
+	uint32_t pllcr;    /* PLL1 control register */
+	uint32_t dllcr;    /* DLL control register */
+	uint32_t hclkgr;   /* HCLK gating register */
+	uint32_t pclkgr;   /* PCLK gating register */
+	uint32_t rsvd1[52];
+
+	/* 0x100 ~ 0x1ff */
+	uint32_t spr[16];  /* Scratchpad register */
+	uint32_t rsvd2[48];
+
+	/* 0x200 ~ 0x2ff */
+	uint32_t gpmux;    /* General PINMUX */
+	uint32_t ehwcfg;   /* Extended HW configuration strap */
+	uint32_t rsvd3[8];
+	uint32_t sccfg[2]; /* Special clock configuration */
+	uint32_t scer;     /* Special clock enable register */
+	uint32_t rsvd;
+	uint32_t mfpmux[2];/* Multi-function pinmux */
+	uint32_t dcsrcr[2];/* Driving cap. & Slew rate control */
+	uint32_t rsvd4[3];
+	uint32_t dccr;     /* Delay chain control register */
+	uint32_t pcr;      /* Power control register */
+};
+
+/* HW configuration strap */
+#define HWCFG_PLL1NS(x)    (((x) >> 5) & 0x3f)
+#define HWCFG_CPUM_MUL(x)  ((((x) >> 3) & 3) > 2 ? 2 : (((x) >> 3) & 3))
+#define HWCFG_DLL_OFF      (1 << 2)
+#define HWCFG_PLL_OFF      (1 << 1)
+#define HWCFG_OSCHCNT_OFF  (1 << 0)
+
+/* Extended HW configuration strap */
+#define EHWCFG_AST         (1 << 15)
+#define EHWCFG_DBG         (1 << 14)
+#define EHWCFG_DBGBYSW     (1 << 13)
+#define EHWCFG_SATA_HOST   (1 << 12)
+#define EHWCFG_PCIE_RC     (1 << 11)
+#define EHWCFG_NAND_BK(x)  (((x) >> 9) & 3)
+#define EHWCFG_NAND_BK16   (0 << 9) /* 16 page per block */
+#define EHWCFG_NAND_BK32   (1 << 9) /* 32 page per block */
+#define EHWCFG_NAND_BK64   (2 << 9) /* 64 page per block */
+#define EHWCFG_NAND_BK128  (3 << 9) /* 128 page per block */
+#define EHWCFG_NAND_PS(x)  (((x) >> 7) & 3)
+#define EHWCFG_NAND_PS512  (0 << 7) /* 512 bytes per page */
+#define EHWCFG_NAND_PS2K   (1 << 7) /* 2048 bytes per page */
+#define EHWCFG_NAND_PS4K   (2 << 7) /* 4096 bytes per page */
+#define EHWCFG_NAND_AC(x)  (((x) >> 5) & 3)
+#define EHWCFG_NAND_AC3    (0 << 5) /* addr cycle = 3 */
+#define EHWCFG_NAND_AC4    (1 << 5) /* addr cycle = 4 */
+#define EHWCFG_NAND_AC5    (2 << 5) /* addr cycle = 5 */
+#define EHWCFG_NAND_16X    (1 << 4) /* NAND: 16bit mode */
+#define EHWCFG_EXTCPU      (1 << 2) /* external cpu mode */
+#define EHWCFG_BOOT_NAND   (0 << 0) /* boot from nand */
+#define EHWCFG_BOOT_SPI    (1 << 0) /* boot from spi */
+#define EHWCFG_BOOT_NOR    (2 << 0) /* boot from nor */
+
+/* General PINMUX */
+#define GPMUX_PLLGMAC      (1 << 15) /* PLL = GMAC PLL(PLL2) */
+#define GPMUX_EXTIRQ       (1 << 14) /* re-direct irq to external cpu */
+#define GPMUX_CS0REL       (1 << 13) /* release CS0 memory space */
+#define GPMUX_IOEN         (1 << 12) /* IO output enable */
+#define GPMUX_CPUS_START   (1 << 11) /* start slave cpu (fa606te) */
+#define GPMUX_SATA_RESET   (1 << 8)
+#define GPMUX_PDD          (1 << 7)  /* power-down detection enable */
+#define GPMUX_USBH_ALIVE   (1 << 6)
+#define GPMUX_USBH_PHYOSC  (1 << 5)
+#define GPMUX_OTG_ALIVE    (1 << 4)
+#define GPMUX_OTG_PHYOSC   (1 << 3)
+#define GPMUX_IRQMASK1     (1 << 2)
+#define GPMUX_IRQMASK0     (1 << 1)
+#define GPMUX_RESET        (1 << 0)
+
+#define GPMUX_DEFAULT      0x1078 /* USB keep alive + IO output */
+
+/* HCLK gating register */
+#define HCLKGR_CPUM        (1 << 31)
+#define HCLKGR_CPUS        (1 << 30)
+#define HCLKGR_AHBTSIF     (1 << 28)
+#define HCLKGR_AHBC3       (1 << 27)
+#define HCLKGR_AHBC2       (1 << 26)
+#define HCLKGR_AHBC1       (1 << 25)
+#define HCLKGR_APBBRG      (1 << 24)
+#define HCLKGR_NANDC       (1 << 23)
+#define HCLKGR_SMC         (1 << 22)
+#define HCLKGR_DMAC1       (1 << 21)
+#define HCLKGR_DMAC0       (1 << 20)
+#define HCLKGR_H264        (1 << 19)
+#define HCLKGR_MPEG4       (1 << 18)
+#define HCLKGR_2DGRA       (1 << 17)
+#define HCLKGR_LCD         (1 << 16)
+#define HCLKGR_ISP         (1 << 15)
+#define HCLKGR_AES         (1 << 14)
+#define HCLKGR_GMAC        (1 << 13)
+#define HCLKGR_SATAH       (1 << 12)
+#define HCLKGR_SATAD       (1 << 11)
+#define HCLKGR_PCIE        (1 << 10)
+#define HCLKGR_USBH        (1 << 9)
+#define HCLKGR_OTG         (1 << 8)
+#define HCLKGR_SD1         (1 << 7)
+#define HCLKGR_SD0         (1 << 6)
+#define HCLKGR_IDE         (1 << 5)
+#define HCLKGR_EM1         (1 << 4)
+#define HCLKGR_EM0         (1 << 3)
+#define HCLKGR_IRQ1        (1 << 2)
+#define HCLKGR_IRQ0        (1 << 1)
+#define HCLKGR_SCU         (1 << 0)
+
+/* Special clock configuration */
+#define SCCFG0_SATA_25M       (1 << 29)
+#define SCCFG0_SATA_OFF       (1 << 28)
+#define SCCFG0_GMAC_CLK_IO    (1 << 27)
+#define SCCFG0_GMAC_PLL_OFF   (1 << 26)
+#define SCCFG0_GMAC_PLL_NS(x) (((x) & 0x3f) << 20)
+#define SCCFG0_ISP_BFREQ(x)   (((x) & 0xf) << 16)
+#define SCCFG0_ISP_AFREQ(x)   (((x) & 0xf) << 12)
+#define SCCFG0_IDE_FREQ(x)    (((x) & 0xf) << 8)
+#define SCCFG0_EXTAHB_FREQ(x) (((x) & 0xf) << 4)
+#define SCCFG0_EXTAHB_MASK    0xf0
+#define SCCFG0_LCD_SCK_AHB    (0 << 2) /* LCD scalar clock source */
+#define SCCFG0_LCD_SCK_APB    (1 << 2)
+#define SCCFG0_LCD_SCK_EXT    (2 << 2)
+#define SCCFG0_LCD_CK_AHB     (0 << 0) /* LCD clock source */
+#define SCCFG0_LCD_CK_APB     (1 << 0)
+#define SCCFG0_LCD_CK_EXT     (2 << 0)
+
+#define SCCFG0_DEFAULT        0x26877330
+
+#define SCCFG1_SD1_CK_2AHB    (0 << 18) /* SD1 clock source */
+#define SCCFG1_SD1_CK_3APB    (1 << 18) /* SD1 clock source */
+#define SCCFG1_SD1_CK_AHB     (2 << 18) /* SD1 clock source */
+#define SCCFG1_SD0_CK_2AHB    (0 << 16) /* SD0 clock source */
+#define SCCFG1_SD0_CK_3APB    (1 << 16) /* SD0 clock source */
+#define SCCFG1_SD0_CK_AHB     (2 << 16) /* SD0 clock source */
+#define SCCFG1_SSP1_CK_EXT    (1 << 12) /* SSP1 clock source */
+#define SCCFG1_SSP1_FREQ(x)   (((x) & 0xf) << 8)
+#define SCCFG1_SSP0_CK_EXT    (1 << 4)  /* SSP0 clock source */
+#define SCCFG1_SSP0_FREQ(x)   (((x) & 0xf) << 0)
+
+#define SCCFG1_DEFAULT \
+	(SCCFG1_SD1_CK_AHB | SCCFG1_SD0_CK_AHB \
+	| SCCFG1_SSP1_FREQ(0xA) | SCCFG1_SSP0_FREQ(0xA))
+
+/* Special clock enable register */
+#define SCER_GMAC125M  (1 << 13)
+#define SCER_LCDSC     (1 << 12) /* LCD scalar clock */
+#define SCER_LCD       (1 << 11)
+#define SCER_ISPB      (1 << 10)
+#define SCER_ISPA      (1 << 9)
+#define SCER_IDE       (1 << 8)
+#define SCER_EXTAHB    (1 << 7)
+#define SCER_DDRD      (1 << 6)
+#define SCER_DDRF      (1 << 5)
+#define SCER_SD1       (1 << 4)
+#define SCER_SD0       (1 << 3)
+#define SCER_SSP1      (1 << 2)
+#define SCER_SSP0      (1 << 1)
+#define SCER_TSC       (1 << 0)
+
+/* Multi-function pinmux register */
+#define MFPMUX0_EBI(x)    (((x) & 0x3) << 10)
+#define MFPMUX0_LCD(x)    (((x) & 0x3) << 8)
+#define MFPMUX0_TS(x)     (((x) & 0x3) << 6)
+#define MFPMUX0_ISP(x)    (((x) & 0x3) << 4)
+#define MFPMUX0_SATA(x)   (((x) & 0x3) << 2)
+#define MFPMUX0_EXTAHB(x) (((x) & 0x3) << 0)
+
+#define MFPMUX0_DEFAULT   0x241 /* SD0 disabled, SD1 enabled */
+
+#define MFPMUX1_KBC(x)    (((x) & 0x3) << 20)
+#define MFPMUX1_GPIO0(x)  (((x) & 0x3) << 18)
+#define MFPMUX1_I2C1(x)   (((x) & 0x3) << 16)
+#define MFPMUX1_PWM1(x)   (((x) & 0x3) << 14)
+#define MFPMUX1_PWM0(x)   (((x) & 0x3) << 12)
+#define MFPMUX1_GMAC(x)   (((x) & 0x3) << 10)
+#define MFPMUX1_SSP1(x)   (((x) & 0x3) << 8)
+#define MFPMUX1_SSP0(x)   (((x) & 0x3) << 6)
+#define MFPMUX1_UART3(x)  (((x) & 0x3) << 4)
+#define MFPMUX1_UART2(x)  (((x) & 0x3) << 2)
+#define MFPMUX1_UART1(x)  (((x) & 0x3) << 0)
+
+/* PLL1 control register */
+#define PLLCR_NS(x)    (((x) >> 24) & 0x3f)
+#define PLLCR_STABLE   (1 << 1)
+#define PLLCR_OFF      (1 << 0)
+
+/* DLL control register */
+#define DLLCR_STABLE   (1 << 1)
+#define DLLCR_ON       (1 << 0)
+
+#endif	/* EOF */
diff --git a/board/faraday/a369evb/Makefile b/board/faraday/a369evb/Makefile
new file mode 100644
index 0000000..42fef70
--- /dev/null
+++ b/board/faraday/a369evb/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= board.o clock.o
+obj-y	+= lowlevel_init.o
diff --git a/board/faraday/a369evb/board.c b/board/faraday/a369evb/board.c
new file mode 100644
index 0000000..cd206bb
--- /dev/null
+++ b/board/faraday/a369evb/board.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#include <spi.h>
+#include <nand.h>
+#include <netdev.h>
+#include <malloc.h>
+
+#include <asm/arch/sysc.h>
+#include <faraday/ftsmc020.h>
+#include <faraday/ftsdc010.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ftsmc020 *smc = (void __iomem *)CONFIG_SMC_BASE;
+static struct sysc_regs *sysc = (void __iomem *)CONFIG_SYSC_BASE;
+
+static void pinmux_init(void)
+{
+	/* If it's an external CPU */
+	if (readl(&sysc->ehwcfg) & EHWCFG_EXTCPU) {
+		writel(HCLKGR_CPUM | HCLKGR_CPUS | HCLKGR_ISP,
+			&sysc->hclkgr);
+		setbits_le32(&sysc->gpmux, GPMUX_EXTIRQ);
+	} else {
+#ifdef CONFIG_A369_EXTAHB
+		/* Enable external AHB */
+		writel(HCLKGR_CPUS, &sysc->hclkgr);
+		writel(GPMUX_DEFAULT, &sysc->gpmux);
+		clrbits_le32(&sysc->sccfg[0], SCCFG0_EXTAHB_MASK);
+		setbits_le32(&sysc->sccfg[0], SCCFG0_EXTAHB_FREQ(8));
+#else
+		/* Enable SD1 */
+		writel(MFPMUX0_DEFAULT, &sysc->mfpmux[0]);
+#endif
+	}
+
+	/* Clock: SD = AHB, SSP = APB (SPI mode) */
+	writel(SCCFG1_DEFAULT, &sysc->sccfg[1]);
+}
+
+/*
+ * Static Memory Controller (NOR Flash)
+ */
+static void smc_init(void)
+{
+	uint32_t nor_base;
+
+	/* Bank 0: NOR flash */
+	if ((readl(&sysc->ehwcfg) & 3) != EHWCFG_BOOT_NOR)
+		nor_base = 0x20000000;
+	else
+		nor_base = 0;
+	writel(FTSMC020_BANK_ENABLE
+		| FTSMC020_BANK_BASE(nor_base) /* base address */
+		| FTSMC020_BANK_SIZE_64M /* window size */
+		| FTSMC020_BANK_MBW_16, /* data width */
+		&smc->bank[0].cr);
+	writel(FTSMC020_TPR_FAILSAFE, &smc->bank[0].tpr);
+
+	/* Bank 1 ~ 3: nothing attached */
+	writel(0, &smc->bank[1].cr);
+	writel(FTSMC020_TPR_FAILSAFE, &smc->bank[1].tpr);
+	writel(0, &smc->bank[2].cr);
+	writel(FTSMC020_TPR_FAILSAFE, &smc->bank[2].tpr);
+	writel(0, &smc->bank[3].cr);
+	writel(FTSMC020_TPR_FAILSAFE, &smc->bank[3].tpr);
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_early_init_f(void)
+{
+	gd->arch.timer_rate_hz = clk_get_rate("APB");
+	pinmux_init();
+	smc_init();
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size  = CONFIG_SYS_SDRAM_SIZE;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+#ifdef CONFIG_USB_ETHER
+	return usb_eth_initialize(bd);
+#elif defined(CONFIG_FTGMAC100)
+	return ftgmac100_initialize(bd);
+#else
+	return 0;
+#endif
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_FTSDC010
+	return ftsdc010_mmc_init(0);
+#else
+	return 0;
+#endif
+}
diff --git a/board/faraday/a369evb/clock.c b/board/faraday/a369evb/clock.c
new file mode 100644
index 0000000..b713b89
--- /dev/null
+++ b/board/faraday/a369evb/clock.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sysc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct sysc_regs *sysc = (void __iomem *)CONFIG_SYSC_BASE;
+
+static inline ulong clk_get_rate_sys(void)
+{
+	return 33000000; /* 33 MHz */
+}
+
+static inline ulong clk_get_rate_ahb(void)
+{
+	return (clk_get_rate_sys() * PLLCR_NS(readl(&sysc->pllcr))) >> 3;
+}
+
+static inline ulong clk_get_rate_apb(void)
+{
+	return clk_get_rate_ahb() >> 1;
+}
+
+static inline ulong clk_get_rate_cpu(void)
+{
+	ulong clk = clk_get_rate_ahb();
+
+	/* If it's an internal CPU */
+	if (readl(&sysc->ehwcfg) & EHWCFG_EXTCPU)
+		return clk;
+	/*
+	 * Since the master would stop immediately after kicking
+	 * off slave cpu, so if GPMUX_CPUS_START is set,
+	 * it must be a slave cpu.
+	 */
+	if (!(readl(&sysc->gpmux) & GPMUX_CPUS_START))
+		clk = clk << HWCFG_CPUM_MUL(readl(&sysc->hwcfg));
+
+	return clk;
+}
+
+ulong clk_get_rate(const char *id)
+{
+	ulong ret = 0;
+
+	if (!strcmp(id, "AHB"))
+		ret = clk_get_rate_ahb();
+	else if (!strcmp(id, "APB"))
+		ret = clk_get_rate_apb();
+	else if (!strcmp(id, "CPU"))
+		ret = clk_get_rate_cpu();
+	else if (!strcmp(id, "I2C"))
+		ret = clk_get_rate_apb();
+	else if (!strcmp(id, "MMC") || !strcmp(id, "SDC"))
+		ret = clk_get_rate_ahb();
+	else if (!strcmp(id, "SPI") || !strcmp(id, "SSP"))
+		ret = clk_get_rate_apb();
+
+	return ret;
+}
diff --git a/board/faraday/a369evb/lowlevel_init.S b/board/faraday/a369evb/lowlevel_init.S
new file mode 100644
index 0000000..2085760
--- /dev/null
+++ b/board/faraday/a369evb/lowlevel_init.S
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+	mov	pc,lr
diff --git a/boards.cfg b/boards.cfg
index 69c8936..49c4f85 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -390,6 +390,7 @@ Active  arm         armv7:arm720t  tegra20     toradex         colibri_t20_iris
 Active  arm         armv7:arm720t  tegra30     avionic-design  tec-ng              tec-ng                               -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
 Active  arm         armv7:arm720t  tegra30     nvidia          beaver              beaver                               -                                                                                                                                 Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra30     nvidia          cardhu              cardhu                               -                                                                                                                                 Tom Warren <twarren@nvidia.com>
+Active  arm         faraday        a369        faraday         a369evb             a369evb                              a369                                                                                                                              Kuo-Jung Su <dantesu@gmail.com>
 Active  arm         pxa            -           -               -                   balloon3                             -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
 Active  arm         pxa            -           -               -                   h2200                                -                                                                                                                                 Lukasz Dalek <luk0104@gmail.com>
 Active  arm         pxa            -           -               -                   palmld                               -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
diff --git a/include/configs/a369.h b/include/configs/a369.h
new file mode 100644
index 0000000..48c6bfa
--- /dev/null
+++ b/include/configs/a369.h
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+/* Support NOR flash */
+/* #define CONFIG_A369_NOR_FLASH */
+
+/* Support USB RNDIS Ethernet */
+/* #define CONFIG_A369_USB_ETHER */
+
+/* Support USB DFU */
+#define CONFIG_A369_USB_DFU
+
+#if defined(CONFIG_A369_USB_ETHER) && defined(CONFIG_A369_USB_DFU)
+# error "USB-ETHER and USB-DFU can't be enabled at the same time."
+#endif
+
+/* Disable MMU/D-CACHE */
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Memory Configuration */
+#define CONFIG_NR_DRAM_BANKS            1
+#define CONFIG_SYS_SDRAM_BASE           0x10000000
+#define CONFIG_SYS_SDRAM_SIZE           SZ_256M
+
+#define CONFIG_SYS_MALLOC_LEN           SZ_2M
+#define CONFIG_SYS_TEXT_BASE            0x10800000
+
+/* Serial (UART) */
+#define CONFIG_FTUART010
+#define CONFIG_FTUART010_CLK            18432000
+#define CONFIG_BAUDRATE                 38400
+
+/* NIC */
+#define CONFIG_FTGMAC100
+
+/* I2C */
+#define CONFIG_FTI2C010
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+
+/* MMC/SD */
+#define CONFIG_FTSDC010
+
+/* NOR flash */
+#ifdef CONFIG_A369_NOR_FLASH
+# define PHYS_FLASH_SIZE                SZ_64M
+# define CONFIG_SYS_FLASH_BASE          0x20000000
+# define CONFIG_SYS_FLASH_CFI_WIDTH     FLASH_CFI_16BIT
+# define CONFIG_SYS_MAX_FLASH_BANKS     1
+# define CONFIG_SYS_MAX_FLASH_SECT      1024
+#endif
+
+/* USB */
+#if defined(CONFIG_A369_USB_DFU) || defined(CONFIG_A369_USB_ETHER)
+# define CONFIG_USB_GADGET
+# define CONFIG_USB_GADGET_FOTG210
+# define CONFIG_USB_GADGET_DUALSPEED
+# define CONFIG_USB_GADGET_VBUS_DRAW        200
+# define CONFIG_USB_MAX_CONTROLLER_COUNT    1
+# define CONFIG_USB_EHCI_BASE               CONFIG_FUSBH200_BASE
+#else
+# define CONFIG_USB_MAX_CONTROLLER_COUNT    2
+# define CONFIG_USB_EHCI_BASE_LIST \
+	{ CONFIG_FUSBH200_BASE, CONFIG_FOTG210_BASE }
+#endif
+
+#ifdef CONFIG_A369_USB_DFU
+# define CONFIG_USBDOWNLOAD_GADGET
+# define CONFIG_DFU_FUNCTION
+# define CONFIG_DFU_RAM
+# define CONFIG_CMD_DFU
+#endif
+
+#ifdef CONFIG_A369_USB_ETHER
+# define CONFIG_USB_ETHER
+# define CONFIG_USB_ETH_RNDIS
+#endif
+
+/* Environment */
+#if defined(CONFIG_A369_NOR_FLASH)
+# define CONFIG_ENV_IS_IN_FLASH /* NOR flash */
+# define CONFIG_ENV_OFFSET          0x3f0000
+#else
+# define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE             SZ_64K
+
+/* Faraday common configuration */
+#include "faraday-common.h"
+
+/* Platform specific environment variables */
+#ifdef CONFIG_A369_USB_DFU
+# define CONFIG_EXTRA_ENV_SETTINGS \
+	/* USB-DFU: [name] [interface] [start] [end] */ \
+	"dfu_alt_info=ram@0x10800000 ram 0x10800000 0x11800000\0"
+#endif
+
+#endif	/* EOF */
diff --git a/include/faraday/ftsmc020.h b/include/faraday/ftsmc020.h
index 54120ab..485d7c2 100644
--- a/include/faraday/ftsmc020.h
+++ b/include/faraday/ftsmc020.h
@@ -70,5 +70,6 @@ void ftsmc020_init(void);
 #define FTSMC020_TPR_WTC(x)	(((x) & 0x3) << 6)
 #define FTSMC020_TPR_AHT(x)	(((x) & 0x3) << 4)
 #define FTSMC020_TPR_TRNA(x)	(((x) & 0xf) << 0)
+#define FTSMC020_TPR_FAILSAFE	0x0f1ff3ff /* fail-safe timing */

 #endif	/* __FTSMC020_H */
