From patchwork Wed Mar 26 06:03:15 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuo-Jung Su X-Patchwork-Id: 333782 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 58C9614009F for ; Wed, 26 Mar 2014 17:04:50 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B2C904B600; Wed, 26 Mar 2014 07:04:48 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nA+bwcoG63J6; Wed, 26 Mar 2014 07:04:48 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 61A564B5FF; Wed, 26 Mar 2014 07:04:45 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A50094B5FF for ; Wed, 26 Mar 2014 07:04:42 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Y9Bu9z-04CoB for ; Wed, 26 Mar 2014 07:04:38 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f169.google.com (mail-pd0-f169.google.com [209.85.192.169]) by theia.denx.de (Postfix) with ESMTPS id 66FA04B5FA for ; Wed, 26 Mar 2014 07:04:32 +0100 (CET) Received: by mail-pd0-f169.google.com with SMTP id fp1so1441501pdb.0 for ; Tue, 25 Mar 2014 23:04:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=G5xkijkKo6gypOGsklZAbMXzblqzFzW8441mqebPhYE=; b=rzL3KRUDcMd9CE5GEDjRqyEnfc7V75raeC5dvvsABdb0VsSFRtIhJbh+dKPFOFRfpY qfvrO8F7caGvCaykbleDs+5sFFonAVkjX/+FToAkDW8KRmPftAlFMSY6h4s/4IW61+IY ezwlxbZTaIYlVyOiEpwLW7GWEV4muYDIfxS9gkZ8C3opl4pFhHfj6iJGJt0VJ/8WeTDw doTC6oIhjjXyEe9/zxHkgET5Asqcx+8K8NvJE5U4LMb4JwyMhNUTT9Sco4PDuFSgMkoy vhH11pcDZL/QyOWbaJqTsGF7LQYE0vwyWAwzK4iE2ckGYEsoYMMFiQZuyM7zusWP9rph B7LQ== X-Received: by 10.68.217.234 with SMTP id pb10mr21384135pbc.142.1395813870050; Tue, 25 Mar 2014 23:04:30 -0700 (PDT) Received: from localhost (42-75-52-36.dynamic-ip.hinet.net. [42.75.52.36]) by mx.google.com with ESMTPSA id vg1sm53266674pbc.44.2014.03.25.23.04.20 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 25 Mar 2014 23:04:29 -0700 (PDT) From: Kuo-Jung Su To: u-boot@lists.denx.de Date: Wed, 26 Mar 2014 14:03:15 +0800 Message-Id: <1395813799-3672-3-git-send-email-dantesu@gmail.com> X-Mailer: git-send-email 1.8.4.msysgit.0 In-Reply-To: <1395813799-3672-1-git-send-email-dantesu@gmail.com> References: <1395813799-3672-1-git-send-email-dantesu@gmail.com> In-Reply-To: <1364540788-13943-1-git-send-email-dantesu@gmail.com> References: <1364540788-13943-1-git-send-email-dantesu@gmail.com> Cc: Kuo-Jung Su Subject: [U-Boot] [PATCH v11 2/6] arm: faraday: add FTTMR010 timer support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Kuo-Jung Su Faraday FTTMR010 is a simple APB device which supports generic timer functions. Signed-off-by: Kuo-Jung Su CC: Albert Aribaud --- Changes for v11: - Directly specify the timer object in 'arch/arm/cpu/faraday//Makefile' instead of using CONFIG_FTTMR010 in 'arch/arm/cpu/faraday/Makefile' Changes for v8, v9, v10: - Nothing updates Changes for v7: - Update license to use SPDX identifiers. Changes for v6: - Nothing updates Changes for v5: - Drop IRQ dependant implementation - Use gd->arch.timer_rate_hz for timer clock source - Use gd->arch.tbl for timestamp Changes for v4: - Coding Style cleanup. - Break up from [arm: add Faraday A36x SoC platform support] Changes for v3: - Coding Style cleanup. - Drop macros for wirtel()/readl(), call them directly. - Always insert a blank line between declarations and code. - Add '__iomem' to all the declaration of HW register pointers. Changes for v2: - Coding Style cleanup. - Use readl(), writel(), clrsetbits_le32() to replace REG() macros. - Use structure based hardware registers to replace the macro constants. - Replace BIT() with BIT_MASK(). arch/arm/cpu/faraday/fttmr010.c | 123 +++++++++++++++++++++++++++++++++++++++ include/faraday/fttmr010.h | 17 ++++++ 2 files changed, 140 insertions(+) create mode 100644 arch/arm/cpu/faraday/fttmr010.c -- 1.7.9.5 diff --git a/arch/arm/cpu/faraday/fttmr010.c b/arch/arm/cpu/faraday/fttmr010.c new file mode 100644 index 0000000..28b0086 --- /dev/null +++ b/arch/arm/cpu/faraday/fttmr010.c @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2013 + * Faraday Technology Corporation. + * Kuo-Jung Su + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct fttmr010 *regs = (void __iomem *)CONFIG_FTTMR010_BASE; + +void udelay_masked(unsigned long usec) +{ + ulong freq = gd->arch.timer_rate_hz; + + /* Disable Timer2 */ + clrbits_le32(®s->cr, FTTMR010_TM2_CRMASK); + /* Disable Timer2 interrupts */ + writel(FTTMR010_TM2_ISRMASK, ®s->interrupt_mask); + /* Clear Timer2 interrupts */ + writel(FTTMR010_TM2_ISRMASK, ®s->interrupt_state); + + /* Configure Timer2 */ + writel((freq / 1000000) * usec, ®s->timer2_counter); + writel(0, ®s->timer2_load); + writel(0, ®s->timer2_match1); + writel(0, ®s->timer2_match2); + + /* Enable Timer2 */ + setbits_le32(®s->cr, + FTTMR010_TM2_OFENABLE | FTTMR010_TM2_ENABLE); + + /* Wait until timeout */ + while (!(readl(®s->interrupt_state) & FTTMR010_TM2_ISRMASK)) + ; +} + +void reset_timer_masked(void) +{ + ulong freq = gd->arch.timer_rate_hz; + + /* Disable Timer1 */ + clrbits_le32(®s->cr, FTTMR010_TM1_CRMASK); + + /* Disable & Clear Timer1 interrupts */ + writel(FTTMR010_TM1_ISRMASK, ®s->interrupt_mask); + writel(FTTMR010_TM1_ISRMASK, ®s->interrupt_state); + + /* Setup a longest periodic timer */ + writel((0xffffffff / freq) * freq, ®s->timer1_counter); + writel((0xffffffff / freq) * freq, ®s->timer1_load); + + writel(0, ®s->timer1_match1); + writel(0, ®s->timer1_match2); + + /* Disable match interrupts */ + writel(FTTMR010_TM1_MATCH1 | FTTMR010_TM1_MATCH2, + ®s->interrupt_mask); + + /* Enable Timer1 with overflow interrupt */ + setbits_le32(®s->cr, + FTTMR010_TM1_OFENABLE | FTTMR010_TM1_ENABLE); +} + +ulong get_timer_masked(void) +{ + ulong freq = gd->arch.timer_rate_hz; + ulong secs = 0xffffffff / freq; + ulong ms = freq / CONFIG_SYS_HZ; + + if (readl(®s->interrupt_state) & FTTMR010_TM1_ISRMASK) { + writel(FTTMR010_TM1_ISRMASK, ®s->interrupt_state); + gd->arch.tbl += secs * CONFIG_SYS_HZ; + } + + return gd->arch.tbl + + ((secs * freq) - readl(®s->timer1_counter)) / ms; +} + +int timer_init(void) +{ + gd->arch.tbl = 0; + reset_timer_masked(); + return 0; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void __udelay(unsigned long usec) +{ + udelay_masked(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/include/faraday/fttmr010.h b/include/faraday/fttmr010.h index 2ab68d1..21ab113 100644 --- a/include/faraday/fttmr010.h +++ b/include/faraday/fttmr010.h @@ -45,6 +45,16 @@ struct fttmr010 { #define FTTMR010_TM1_CLOCK (1 << 1) #define FTTMR010_TM1_ENABLE (1 << 0) +#define FTTMR010_TM1_CRMASK \ + (FTTMR010_TM1_UPDOWN | FTTMR010_TM1_OFENABLE \ + | FTTMR010_TM1_CLOCK | FTTMR010_TM1_ENABLE) +#define FTTMR010_TM2_CRMASK \ + (FTTMR010_TM2_UPDOWN | FTTMR010_TM2_OFENABLE \ + | FTTMR010_TM2_CLOCK | FTTMR010_TM2_ENABLE) +#define FTTMR010_TM3_CRMASK \ + (FTTMR010_TM3_UPDOWN | FTTMR010_TM3_OFENABLE \ + | FTTMR010_TM3_CLOCK | FTTMR010_TM3_ENABLE) + /* * Timer Interrupt State & Mask Registers */ @@ -58,4 +68,11 @@ struct fttmr010 { #define FTTMR010_TM1_MATCH2 (1 << 1) #define FTTMR010_TM1_MATCH1 (1 << 0) +#define FTTMR010_TM1_ISRMASK \ + (FTTMR010_TM1_OVERFLOW | FTTMR010_TM1_MATCH2 | FTTMR010_TM1_MATCH1) +#define FTTMR010_TM2_ISRMASK \ + (FTTMR010_TM2_OVERFLOW | FTTMR010_TM2_MATCH2 | FTTMR010_TM2_MATCH1) +#define FTTMR010_TM3_ISRMASK \ + (FTTMR010_TM3_OVERFLOW | FTTMR010_TM3_MATCH2 | FTTMR010_TM3_MATCH1) + #endif /* __FTTMR010_H */