| Message ID | 1394277305-18862-1-git-send-email-prabhakar@freescale.com |
|---|---|
| State | Accepted |
| Delegated to: | York Sun |
| Headers | show |
On 03/08/2014 03:15 AM, Prabhakar Kushwaha wrote: > The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher > than 2.5 MHZ. It violates the IEEE specs. > > So Slow MDC clock to comply IEEE specs > > Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> > --- > Changes for v2: Update commit message Applied to u-boot-mpc85xx/master, thanks. York
diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg index 57b726e..05377ba 100644 --- a/board/freescale/b4860qds/b4_pbi.cfg +++ b/board/freescale/b4860qds/b4_pbi.cfg @@ -22,6 +22,9 @@ 09110024 00100008 09110028 00100008 0911002c 00100008 +#slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 #Flush PBL data 09138000 00000000 091380c0 00000000
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs. So Slow MDC clock to comply IEEE specs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> --- Changes for v2: Update commit message board/freescale/b4860qds/b4_pbi.cfg | 3 +++ 1 file changed, 3 insertions(+)