From patchwork Wed Mar 5 19:01:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 327119 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 082A82C0084 for ; Thu, 6 Mar 2014 06:01:33 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C55AB4B610; Wed, 5 Mar 2014 20:01:31 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UIQBnyfjtC-b; Wed, 5 Mar 2014 20:01:31 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8DE894B5E4; Wed, 5 Mar 2014 20:01:28 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9ABE84B5E9 for ; Wed, 5 Mar 2014 20:01:26 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id H0s0B27HHArS for ; Wed, 5 Mar 2014 20:01:23 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10]) by theia.denx.de (Postfix) with ESMTPS id 5DE624B5D5 for ; Wed, 5 Mar 2014 20:01:20 +0100 (CET) Received: from frontend1.mail.m-online.net (frontend1.mail.intern.m-online.net [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 3ffPZR5ZNtz3hjKh; Wed, 5 Mar 2014 20:01:19 +0100 (CET) X-Auth-Info: 143oOP/Jyn+W+JCLu/nJt4SHD1gdrSPArun/qJ/87/4= Received: from chi.lan (host-82-135-33-74.customer.m-online.net [82.135.33.74]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 3ffPZR3dRFzbbg3; Wed, 5 Mar 2014 20:01:19 +0100 (CET) From: Marek Vasut To: u-boot@lists.denx.de Date: Wed, 5 Mar 2014 20:01:13 +0100 Message-Id: <1394046074-6389-1-git-send-email-marex@denx.de> X-Mailer: git-send-email 1.8.5.3 Cc: Marek Vasut Subject: [U-Boot] [PATCH 1/2] arm: mxs: Adjust the load address of U-Boot and SPL for HAB X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de When using HAB, there are additional special requirements on the placement of U-Boot and the U-Boot SPL in memory. To fullfill these, this patch moves the U-Boot binary a little further from the begining of the DRAM, so the HAB CST and IVT can be placed in front of the U-Boot binary. This is necessary, since both the U-Boot and the IVT must be contained in single CST signature. To make things worse, the IVT must be concatenated with one more entry at it's end, that is the length of the entire CST signature, IVT and U-Boot binary in memory. By placing the blocks in this order -- CST, IVT, U-Boot, we can easily align them all and then produce the length field as needed. As for the SPL, on i.MX23/i.MX28, the SPL size is limited to 32 KiB, thus we place the IVT at 0x8000 offset, CST right past IVT and claim the size is correct. The HAB library accepts this setup. Finally, to make sure the vectoring in SPL still works even after moving the SPL from 0x0 to 0x1000, we add a small function which copies the vectoring code and tables to 0x0. This is fine, since the vectoring code is position independent. Signed-off-by: Marek Vasut Cc: Stefano Babic --- arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg | 8 ++++---- arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg | 8 ++++---- arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 15 +++++++++++++++ arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds | 2 +- include/configs/mxs.h | 10 +++++++++- 5 files changed, 33 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg index c9cf4b3..70abfbc 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg @@ -1,6 +1,6 @@ SECTION 0x0 BOOTABLE TAG LAST - LOAD 0x0 OBJTREE/spl/u-boot-spl.bin - CALL 0x14 0x0 - LOAD 0x40000100 OBJTREE/u-boot.bin - CALL 0x40000100 0x0 + LOAD 0x1000 OBJTREE/spl/u-boot-spl.bin + CALL 0x1000 0x0 + LOAD 0x40002000 OBJTREE/u-boot.bin + CALL 0x40002000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg index 676f5c8..e98c97b 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg @@ -1,8 +1,8 @@ SECTION 0x0 BOOTABLE TAG LAST - LOAD 0x0 OBJTREE/spl/u-boot-spl.bin - LOAD IVT 0x8000 0x14 + LOAD 0x1000 OBJTREE/spl/u-boot-spl.bin + LOAD IVT 0x8000 0x1000 CALL HAB 0x8000 0x0 - LOAD 0x40000100 OBJTREE/u-boot.bin - LOAD IVT 0x8000 0x40000100 + LOAD 0x40002000 OBJTREE/u-boot.bin + LOAD IVT 0x8000 0x40002000 CALL HAB 0x8000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 68c30af..38109c5 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -102,6 +102,18 @@ static uint8_t mxs_get_bootmode_index(void) return i; } +static void mxs_spl_fixup_vectors(void) +{ + /* + * Copy our vector table to 0x0, since due to HAB, we cannot + * be loaded to 0x0. We want to have working vectoring though, + * thus this fixup. Our vectoring table is PIC, so copying is + * fine. + */ + extern uint32_t _start; + memcpy(0x0, &_start, 0x60); +} + void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, const iomux_cfg_t *iomux_setup, const unsigned int iomux_size) @@ -110,7 +122,10 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); uint8_t bootmode = mxs_get_bootmode_index(); + mxs_spl_fixup_vectors(); + mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size); + mxs_power_init(); mxs_mem_init(); diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index d0b482d..f4bf8ac 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -16,7 +16,7 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { - . = 0x00000000; + . = CONFIG_SPL_TEXT_BASE; . = ALIGN(4); .text : diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 55ecef9..a9f4d89 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -80,8 +80,16 @@ * We need to sacrifice first 4 bytes of RAM here to avoid triggering some * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot * binary. In case there was more of this mess, 0x100 bytes are skipped. + * + * In case of a HAB boot, we cannot for some weird reason use the first 4KiB + * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST + * blocks, thus U-Boot starts at offset +8 KiB of DRAM start. + * + * As for the SPL, we must avoid the first 4 KiB as well, but we load the + * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB. */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 +#define CONFIG_SYS_TEXT_BASE 0x40002000 +#define CONFIG_SPL_TEXT_BASE 0x00001000 /* U-Boot general configuration */ #define CONFIG_SYS_LONGHELP