From patchwork Sat Feb 22 07:56:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar Kushwaha X-Patchwork-Id: 323131 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 52DFA2C020F for ; Sat, 22 Feb 2014 18:57:27 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8DBA64B7CA; Sat, 22 Feb 2014 08:57:25 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uOaIPCLNlQYh; Sat, 22 Feb 2014 08:57:25 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4C4874B7CC; Sat, 22 Feb 2014 08:57:21 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 636E04B7CC for ; Sat, 22 Feb 2014 08:57:16 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wF3G48-gauqN for ; Sat, 22 Feb 2014 08:57:14 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from co9outboundpool.messaging.microsoft.com (co9ehsobe004.messaging.microsoft.com [207.46.163.27]) by theia.denx.de (Postfix) with ESMTPS id 6FC1C4B7CA for ; Sat, 22 Feb 2014 08:57:10 +0100 (CET) Received: from mail89-co9-R.bigfish.com (10.236.132.240) by CO9EHSOBE001.bigfish.com (10.236.130.64) with Microsoft SMTP Server id 14.1.225.22; Sat, 22 Feb 2014 07:57:08 +0000 Received: from mail89-co9 (localhost [127.0.0.1]) by mail89-co9-R.bigfish.com (Postfix) with ESMTP id 7DE24B40528 for ; Sat, 22 Feb 2014 07:57:08 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: -1 X-BigFish: VS-1(zz1454Ie0eahzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah21bch1fc6hzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h24afh2327h2336h2438h2461h2487h24d7h2516h2545h255eh1155h) Received: from mail89-co9 (localhost.localdomain [127.0.0.1]) by mail89-co9 (MessageSwitch) id 1393055825790446_24910; Sat, 22 Feb 2014 07:57:05 +0000 (UTC) Received: from CO9EHSMHS014.bigfish.com (unknown [10.236.132.241]) by mail89-co9.bigfish.com (Postfix) with ESMTP id AF4A2D40062; Sat, 22 Feb 2014 07:57:05 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO9EHSMHS014.bigfish.com (10.236.130.24) with Microsoft SMTP Server (TLS) id 14.16.227.3; Sat, 22 Feb 2014 07:57:04 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.3.158.2; Sat, 22 Feb 2014 07:57:02 +0000 Received: from b32579-VirtualBox.ap.freescale.net (B32579-02-010232132053.ap.freescale.net [10.232.132.53]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s1M7utNJ000724; Sat, 22 Feb 2014 00:57:01 -0700 From: Prabhakar Kushwaha To: Date: Sat, 22 Feb 2014 13:26:54 +0530 Message-ID: <1393055814-6047-1-git-send-email-prabhakar@freescale.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-FOPE-CONNECTOR: Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn% Cc: yorksun@freescale.com Subject: [U-Boot] [PATCH] board/t104xrdb: Add support of CPLD X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features. This support of CPLD includes - files and register defintion - Commands to swtich alternate bank and default bank Signed-off-by: Prabhakar Kushwaha --- board/freescale/t104xrdb/Makefile | 1 + board/freescale/t104xrdb/cpld.c | 113 +++++++++++++++++++++++++++++++++++ board/freescale/t104xrdb/cpld.h | 40 +++++++++++++ board/freescale/t104xrdb/t104xrdb.c | 13 ++++ include/configs/T1040RDB.h | 8 +++ include/configs/T1042RDB_PI.h | 8 +++ 6 files changed, 183 insertions(+) create mode 100644 board/freescale/t104xrdb/cpld.c create mode 100644 board/freescale/t104xrdb/cpld.h diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile index e51fb7a..af38d9f 100644 --- a/board/freescale/t104xrdb/Makefile +++ b/board/freescale/t104xrdb/Makefile @@ -11,3 +11,4 @@ obj-y += eth.o obj-$(CONFIG_PCI) += pci.o obj-y += law.o obj-y += tlb.o +obj-y += cpld.o diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c new file mode 100644 index 0000000..4443a04 --- /dev/null +++ b/board/freescale/t104xrdb/cpld.c @@ -0,0 +1,113 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map + */ + +#include +#include +#include + +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); + printf("reset_ctl[0] = 0x%02x\n", CPLD_READ(reset_ctl[0])); + printf("reset_ctl[1] = 0x%02x\n", CPLD_READ(reset_ctl[1])); + printf("int_status = 0x%02x\n", CPLD_READ(int_status)); + printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); + printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); + printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status)); + printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); + printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); + printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); + printf("boot_config[0] = 0x%02x\n", CPLD_READ(boot_config[0])); + printf("boot_config[1] = 0x%02x\n", CPLD_READ(boot_config[1])); + printf("boot_config[2] = 0x%02x\n", CPLD_READ(boot_config[2])); + putc('\n'); +} +#endif + +int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd, + "Reset the board or alternate bank", + "reset - hard reset to default bank\n" + "cpld_cmd reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "cpld_cmd dump - display the CPLD registers\n" +#endif + ); diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h new file mode 100644 index 0000000..463b3db --- /dev/null +++ b/board/freescale/t104xrdb/cpld.h @@ -0,0 +1,40 @@ +/** + * Copyright 2013 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl1; /* 0x10 - Reset control Register1 */ + u8 reset_ctl2; /* 0x11 - Reset control Register2 */ + u8 int_status; /* 0x12 - Interrupt status Register */ + u8 flash_ctl_status; /* 0x13 - Flash control and status register */ + u8 fan_ctl_status; /* 0x14 - Fan control and status register */ + u8 led_ctl_status; /* 0x15 - LED control and status register */ + u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ + u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ + u8 boot_override; /* 0x18 - Boot override register */ + u8 boot_config1; /* 0x19 - Boot config override register*/ + u8 boot_confi2; /* 0x1A - Boot config override register*/ +} cpld_data_t; + + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value)\ + cpld_write(offsetof(struct cpld_data, reg), value) diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 6e29d64..b48133a 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -19,14 +19,27 @@ #include #include "t104xrdb.h" +#include "cpld.h" DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; + u8 sw; printf("Board: %sRDB\n", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_ver)); + + sw = CPLD_READ(flash_ctl_status); + sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + + if (sw <= 7) + printf("vBank: %d\n", sw); + else + printf("Unsupported Bank=%x\n", sw); + return 0; } diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index 0f79896..cf04c79 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -195,6 +195,14 @@ #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} /* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 + #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) #define CONFIG_SYS_CSPR2_EXT (0xf) diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index 76cbdea..e622ae3 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -195,6 +195,14 @@ #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} /* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 + #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) #define CONFIG_SYS_CSPR2_EXT (0xf)