From patchwork Tue Feb 18 05:52:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Qiang X-Patchwork-Id: 321283 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5C0B12C00D2 for ; Tue, 18 Feb 2014 16:56:32 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 36B224B7D9; Tue, 18 Feb 2014 06:56:30 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CDBbncPljqtI; Tue, 18 Feb 2014 06:56:29 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5CCAD4B7DF; Tue, 18 Feb 2014 06:56:26 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 532014B7DF for ; Tue, 18 Feb 2014 06:56:22 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Hbucqzdd+QGU for ; Tue, 18 Feb 2014 06:56:19 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe006.messaging.microsoft.com [216.32.181.186]) by theia.denx.de (Postfix) with ESMTPS id 401144B7D9 for ; Tue, 18 Feb 2014 06:56:16 +0100 (CET) Received: from mail33-ch1-R.bigfish.com (10.43.68.227) by CH1EHSOBE008.bigfish.com (10.43.70.58) with Microsoft SMTP Server id 14.1.225.22; Tue, 18 Feb 2014 05:56:14 +0000 Received: from mail33-ch1 (localhost [127.0.0.1]) by mail33-ch1-R.bigfish.com (Postfix) with ESMTP id 94BA740233 for ; Tue, 18 Feb 2014 05:56:14 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 7 X-BigFish: VS7(zza1fflzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6h1082kzz1de098h8275bh1de097hz2dh2a8h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h24afh2327h2336h2438h2461h2487h24d7h2516h2545h255eh1155h) Received: from mail33-ch1 (localhost.localdomain [127.0.0.1]) by mail33-ch1 (MessageSwitch) id 1392702972730044_5740; Tue, 18 Feb 2014 05:56:12 +0000 (UTC) Received: from CH1EHSMHS027.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.240]) by mail33-ch1.bigfish.com (Postfix) with ESMTP id 8AE5C2A005F; Tue, 18 Feb 2014 05:56:12 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS027.bigfish.com (10.43.70.27) with Microsoft SMTP Server (TLS) id 14.16.227.3; Tue, 18 Feb 2014 05:56:12 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.3.158.2; Tue, 18 Feb 2014 05:56:11 +0000 Received: from titan.ap.freescale.net (titan.ap.freescale.net [10.192.208.233]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s1I5u8jH003951; Mon, 17 Feb 2014 22:56:09 -0700 From: Zhao Qiang To: , Date: Tue, 18 Feb 2014 13:52:37 +0800 Message-ID: <1392702757-9296-1-git-send-email-B45475@freescale.com> X-Mailer: git-send-email 1.8.5 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-FOPE-CONNECTOR: Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn% Cc: Zhao Qiang , R63061@freescale.com Subject: [U-Boot] [PATCH v4 2/2] Powerpc/QE: Add QE support for T1040 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The u-qe of T1040 has addresses different from qe, modify those addresses value for both u-qe and qe. Add function qe_board_setup to mux the bus to tdm or uart according to hwconfig. Signed-off-by: Zhao Qiang --- Changes for v2: - modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR Changes for v3: - use CONFIG_U_QE instead of CONFIG_PPC_T1040 Changes for v4: - ifdef CONFIG_U_QE, include "../../../../drivers/qe/qe.h" arch/powerpc/cpu/mpc85xx/cpu_init.c | 11 +++++++++++ arch/powerpc/cpu/mpc85xx/qe_io.c | 2 +- arch/powerpc/cpu/mpc85xx/speed.c | 6 ++++++ arch/powerpc/cpu/mpc85xx/t1040_ids.c | 1 + arch/powerpc/include/asm/config_mpc85xx.h | 3 +++ arch/powerpc/include/asm/fsl_liodn.h | 4 ++++ arch/powerpc/include/asm/immap_85xx.h | 5 ++++- board/freescale/t1040qds/t1040qds.c | 29 +++++++++++++++++++++++++++++ drivers/qe/qe.h | 2 ++ include/configs/T1040QDS.h | 3 +++ 10 files changed, 64 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index ec6eefb..fab5658 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -33,10 +33,14 @@ #endif #include "../../../../drivers/block/fsl_sata.h" +#ifdef CONFIG_U_QE +#include "../../../../drivers/qe/qe.h" +#endif DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_QE +#ifndef CONFIG_U_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); @@ -59,6 +63,7 @@ static void config_qe_ioports(void) } } #endif +#endif #ifdef CONFIG_CPM2 void config_8560_ioports (volatile ccsr_cpm_t * cpm) @@ -262,9 +267,11 @@ void cpu_init_f (void) m8560_cpm_reset(); #endif #ifdef CONFIG_QE +#ifndef CONFIG_U_QE /* Config QE ioports */ config_qe_ioports(); #endif +#endif #if defined(CONFIG_FSL_DMA) dma_init(); #endif @@ -736,7 +743,11 @@ int sata_initialize(void) void cpu_secondary_init_r(void) { #ifdef CONFIG_QE +#ifdef CONFIG_U_QE + uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ +#else uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ +#endif #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND int ret; size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c index 76c60da..d2825ec 100644 --- a/arch/powerpc/cpu/mpc85xx/qe_io.c +++ b/arch/powerpc/cpu/mpc85xx/qe_io.c @@ -12,7 +12,7 @@ #include "asm/io.h" #include "asm/immap_85xx.h" -#if defined(CONFIG_QE) +#if defined(CONFIG_QE) && !defined(CONFIG_U_QE) #define NUM_OF_PINS 32 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) { diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 35867df..634f107 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -335,6 +335,12 @@ void get_sys_info(sys_info_t *sys_info) #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ +#ifdef CONFIG_QE +#if defined(CONFIG_PPC_T1040) + sys_info->freq_qe = sys_info->freq_systembus / 2; +#endif +#endif + #else /* CONFIG_FSL_CORENET */ uint plat_ratio, e500_ratio, half_freq_systembus; int i; diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index 32075ce..4984727 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -66,6 +66,7 @@ struct liodn_id_table liodn_tbl[] = { SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), /* SET_NEXUS_LIODN(557), -- not yet implemented */ + SET_QE_LIODN(559), }; int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index be1d9d2..7d21c84 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -721,6 +721,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 44bc88d..f658bcb 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -99,6 +99,10 @@ extern void fdt_fixup_liodn(void *blob); SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\ CONFIG_SYS_MPC85xx_ESDHC_OFFSET) +#define SET_QE_LIODN(liodn) \ + SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\ + CONFIG_SYS_MPC85xx_QE_OFFSET) + #define SET_QMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \ CONFIG_SYS_FSL_QMAN_OFFSET, \ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 68c3c82..ec6c655 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1871,7 +1871,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) u32 sata2liodnr; /* SATA 2 LIODN */ u32 sata3liodnr; /* SATA 3 LIODN */ u32 sata4liodnr; /* SATA 4 LIODN */ - u8 res22[32]; + u8 res22[24]; + u32 qeliodnr; /* QE LIODN */ + u8 res_57c[4]; u32 dma1liodnr; /* DMA 1 LIODN */ u32 dma2liodnr; /* DMA 2 LIODN */ u32 dma3liodnr; /* DMA 3 LIODN */ @@ -2843,6 +2845,7 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 +#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\ && !defined(CONFIG_PPC_B4420) diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index de3ea5c..4d18fb5 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "t1040qds.h" @@ -89,6 +90,30 @@ int select_i2c_ch_pca9547(u8 ch) return 0; } +static void qe_board_setup(void) +{ + u8 brdcfg15, brdcfg9; + + if (hwconfig("qe") && hwconfig("tdm")) { + brdcfg15 = QIXIS_READ(brdcfg[15]); + /* + * TDMRiser uses QE-TDM + * Route QE_TDM signals to TDM Riser slot + */ + QIXIS_WRITE(brdcfg[15], brdcfg15 | 7); + } else if (hwconfig("qe") && hwconfig("uart")) { + brdcfg15 = QIXIS_READ(brdcfg[15]); + brdcfg9 = QIXIS_READ(brdcfg[9]); + /* + * Route QE_TDM signals to UCC + * ProfiBus controlled by UCC3 + */ + brdcfg15 &= 0xfc; + QIXIS_WRITE(brdcfg[15], brdcfg15 | 2); + QIXIS_WRITE(brdcfg[9], brdcfg9 | 4); + } +} + int board_early_init_r(void) { #ifdef CONFIG_SYS_FLASH_BASE @@ -196,6 +221,10 @@ int misc_init_r(void) } } +#if defined(CONFIG_QE) + qe_board_setup(); +#endif + return 0; } diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index c82ac7b..2079bf6 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -282,5 +282,7 @@ int qe_set_mii_clk_src(int ucc_num); int qe_upload_firmware(const struct qe_firmware *firmware); struct qe_firmware_info *qe_get_firmware_info(void); void ft_qe_setup(void *blob); +extern void qe_init(uint qe_base); +extern void qe_reset(void); #endif /* __QE_H__ */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 0282922..a2124b1 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -572,6 +572,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME +#define CONFIG_QE +#define CONFIG_U_QE /* Default address of microcode for the Linux Fman driver */ #if defined(CONFIG_SPIFLASH) /* @@ -594,6 +596,7 @@ unsigned long get_board_ddr_clk(void); #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)