From patchwork Tue Jan 28 14:54:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 314731 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 2C70E2C00AD for ; Wed, 29 Jan 2014 01:54:56 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 61D9F4B200; Tue, 28 Jan 2014 15:54:53 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XLToQqkh8m9L; Tue, 28 Jan 2014 15:54:53 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8630D4B210; Tue, 28 Jan 2014 15:54:48 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2A3E44B200 for ; Tue, 28 Jan 2014 15:54:46 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KO-WnADohgxO for ; Tue, 28 Jan 2014 15:54:40 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from co1outboundpool.messaging.microsoft.com (co1ehsobe004.messaging.microsoft.com [216.32.180.187]) by theia.denx.de (Postfix) with ESMTPS id 6B76B4B1EB for ; Tue, 28 Jan 2014 15:54:33 +0100 (CET) Received: from mail130-co1-R.bigfish.com (10.243.78.249) by CO1EHSOBE038.bigfish.com (10.243.66.103) with Microsoft SMTP Server id 14.1.225.22; Tue, 28 Jan 2014 14:54:30 +0000 Received: from mail130-co1 (localhost [127.0.0.1]) by mail130-co1-R.bigfish.com (Postfix) with ESMTP id 8733B940223; Tue, 28 Jan 2014 14:54:30 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah21bch1fc6hzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h24afh2327h2336h2438h2461h2487h24d7h1155h) Received: from mail130-co1 (localhost.localdomain [127.0.0.1]) by mail130-co1 (MessageSwitch) id 1390920867702489_7366; Tue, 28 Jan 2014 14:54:27 +0000 (UTC) Received: from CO1EHSMHS002.bigfish.com (unknown [10.243.78.225]) by mail130-co1.bigfish.com (Postfix) with ESMTP id 9D6E130004F; Tue, 28 Jan 2014 14:54:27 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO1EHSMHS002.bigfish.com (10.243.66.12) with Microsoft SMTP Server (TLS) id 14.16.227.3; Tue, 28 Jan 2014 14:54:26 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-004.039d.mgd.msft.net (10.84.1.14) with Microsoft SMTP Server (TLS) id 14.3.158.2; Tue, 28 Jan 2014 14:54:26 +0000 Received: from fabio-Latitude-E6410.am.freescale.net ([10.29.244.105]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s0SEsNhE015113; Tue, 28 Jan 2014 07:54:24 -0700 From: Fabio Estevam To: Date: Tue, 28 Jan 2014 12:54:20 -0200 Message-ID: <1390920860-12153-1-git-send-email-fabio.estevam@freescale.com> X-Mailer: git-send-email 1.8.1.2 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-FOPE-CONNECTOR: Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn% Cc: Fabio Estevam , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3] mx6: Enable L2 cache support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add L2 cache support and enable it by default. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic --- Changes since v2: - Add L2_PL310_BASE definition in imx_regs.h Changes since v1: - Fx typo in commit log arch/arm/cpu/armv7/mx6/soc.c | 20 ++++++++++++++++++++ arch/arm/include/asm/arch-mx6/imx-regs.h | 1 + include/configs/mx6_common.h | 5 +++++ 3 files changed, 26 insertions(+) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 0208cba..b84de87 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -8,6 +8,8 @@ */ #include +#include +#include #include #include #include @@ -336,3 +338,21 @@ void imx_setup_hdmi(void) writel(reg, &mxc_ccm->chsccdr); } #endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +#define L2CACHE 1 +void v7_outer_cache_enable(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; + + setbits_le32(&pl310->pl310_ctrl, L2CACHE); + +} + +void v7_outer_cache_disable(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; + + clrbits_le32(&pl310->pl310_ctrl, L2CACHE); +} +#endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index f2ad6e9..c2d210a 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -53,6 +53,7 @@ #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 +#define L2_PL310_BASE 0x00A02000 #define GPV0_BASE_ADDR 0x00B00000 #define GPV1_BASE_ADDR 0x00C00000 #define PCIE_ARB_BASE_ADDR 0x01000000 diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 514d634..63afa46 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -22,4 +22,9 @@ #define CONFIG_ARM_ERRATA_751472 #define CONFIG_BOARD_POSTCLK_INIT +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#endif + #endif