From patchwork Wed Jan 22 20:20:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 313403 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id F1C102C00AD for ; Thu, 23 Jan 2014 07:21:48 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 343B84B31A; Wed, 22 Jan 2014 21:21:32 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LluNGBfPKLcn; Wed, 22 Jan 2014 21:21:32 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2C6364B231; Wed, 22 Jan 2014 21:21:02 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 43C4E4B1F7 for ; Wed, 22 Jan 2014 21:20:57 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ySlKEKfOvk9I for ; Wed, 22 Jan 2014 21:20:56 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from avon.wwwdotorg.org (avon.wwwdotorg.org [70.85.31.133]) by theia.denx.de (Postfix) with ESMTPS id 5486B4B1FD for ; Wed, 22 Jan 2014 21:20:50 +0100 (CET) Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id 6F21E6448; Wed, 22 Jan 2014 13:20:48 -0700 (MST) Received: from swarren-lx1.nvidia.com (localhost [127.0.0.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id 6416EE4610; Wed, 22 Jan 2014 13:20:33 -0700 (MST) From: Stephen Warren To: u-boot@lists.denx.de, Simon Glass , Tom Warren , Stephen Warren Date: Wed, 22 Jan 2014 13:20:36 -0700 Message-Id: <1390422036-31947-6-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1390422036-31947-1-git-send-email-swarren@wwwdotorg.org> References: <1390422036-31947-1-git-send-email-swarren@wwwdotorg.org> X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.97.8 at avon.wwwdotorg.org X-Virus-Status: Clean Cc: Tom Warren Subject: [U-Boot] [PATCH 6/6] ARM: tegra: implement MASK_BITS_31_29 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Tom Warren Some clock sources have 3-bit muxes in bits 31:29. Implement core support for this mux field. Signed-off-by: Tom Warren [swarren, extracted from a larger patch by Tom] Signed-off-by: Stephen Warren --- arch/arm/cpu/tegra-common/clock.c | 22 ++++++++++++++++++---- arch/arm/include/asm/arch-tegra/clk_rst.h | 3 +++ 2 files changed, 21 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c index 96b705f2f6a4..33bb19084b8c 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/cpu/tegra-common/clock.c @@ -304,13 +304,27 @@ static int adjust_periph_pll(enum periph_id periph_id, int source, /* work out the source clock and set it */ if (source < 0) return -1; - if (mux_bits == MASK_BITS_31_28) { - clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK, - source << OUT_CLK_SOURCE_31_28_SHIFT); - } else { + + switch (mux_bits) { + case MASK_BITS_31_30: clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK, source << OUT_CLK_SOURCE_31_30_SHIFT); + break; + + case MASK_BITS_31_29: + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK, + source << OUT_CLK_SOURCE_31_29_SHIFT); + break; + + case MASK_BITS_31_28: + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK, + source << OUT_CLK_SOURCE_31_28_SHIFT); + break; + + default: + return -1; } + udelay(2); return 0; } diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 9f81237d2865..f07b83d26af4 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -236,6 +236,9 @@ enum { #define OUT_CLK_SOURCE_31_30_SHIFT 30 #define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT) +#define OUT_CLK_SOURCE_31_29_SHIFT 29 +#define OUT_CLK_SOURCE_31_29_MASK (7U << OUT_CLK_SOURCE_31_29_SHIFT) + /* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */ #define OUT_CLK_SOURCE_31_28_SHIFT 28 #define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT)