@@ -43,14 +43,19 @@ u32 get_cpu_rev(void)
if (type != MXC_CPU_MX6SL) {
reg = readl(&anatop->digprog);
+ struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+ u32 cfg = readl(&scu->config) & 3;
type = ((reg >> 16) & 0xff);
if (type == MXC_CPU_MX6DL) {
- struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
- u32 cfg = readl(&scu->config) & 3;
-
if (!cfg)
type = MXC_CPU_MX6SOLO;
}
+
+ if (type == MXC_CPU_MX6Q) {
+ if (cfg == 1)
+ type = MXC_CPU_MX6D;
+ }
+
}
reg &= 0xff; /* mx6 silicon revision */
return (type << 12) | (reg + 0x10);
@@ -64,6 +69,9 @@ u32 __weak get_board_rev(void)
if (type == MXC_CPU_MX6SOLO)
cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
+ if (type == MXC_CPU_MX6D)
+ cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
+
return cpurev;
}
#endif
@@ -106,6 +106,8 @@ const char *get_imx_type(u32 imxtype)
switch (imxtype) {
case MXC_CPU_MX6Q:
return "6Q"; /* Quad-core version of the mx6 */
+ case MXC_CPU_MX6D:
+ return "6D"; /* Dual-core version of the mx6 */
case MXC_CPU_MX6DL:
return "6DL"; /* Dual Lite version of the mx6 */
case MXC_CPU_MX6SOLO:
@@ -16,6 +16,7 @@
#define MXC_CPU_MX6DL 0x61
#define MXC_CPU_MX6SOLO 0x62
#define MXC_CPU_MX6Q 0x63
+#define MXC_CPU_MX6D 0x64
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
u32 get_cpu_rev(void);