From patchwork Tue Dec 31 00:26:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin Liang See X-Patchwork-Id: 305834 X-Patchwork-Delegate: panto@antoniou-consulting.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4D84B2C0099 for ; Tue, 31 Dec 2013 11:26:42 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CB0814AB62; Tue, 31 Dec 2013 01:26:40 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id c9ogUnA8zWGJ; Tue, 31 Dec 2013 01:26:40 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 732E74AB69; Tue, 31 Dec 2013 01:26:37 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 330F34AB69 for ; Tue, 31 Dec 2013 01:26:35 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GPhEI9-C6PJL for ; Tue, 31 Dec 2013 01:26:33 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from db8outboundpool.messaging.microsoft.com (mail-db8lp0187.outbound.messaging.microsoft.com [213.199.154.187]) by theia.denx.de (Postfix) with ESMTPS id 5B0064AB62 for ; Tue, 31 Dec 2013 01:26:31 +0100 (CET) Received: from mail83-db8-R.bigfish.com (10.174.8.241) by DB8EHSOBE004.bigfish.com (10.174.4.67) with Microsoft SMTP Server id 14.1.225.22; Tue, 31 Dec 2013 00:26:29 +0000 Received: from mail83-db8 (localhost [127.0.0.1]) by mail83-db8-R.bigfish.com (Postfix) with ESMTP id B2645100266; Tue, 31 Dec 2013 00:26:29 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.231; KIP:(null); UIP:(null); IPV:NLI; H:sj-itexedge01.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2fh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah224fh1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e1dh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received-SPF: pass (mail83-db8: domain of altera.com designates 66.35.236.231 as permitted sender) client-ip=66.35.236.231; envelope-from=clsee@altera.com; helo=sj-itexedge01.altera.priv.altera.com ; v.altera.com ; Received: from mail83-db8 (localhost.localdomain [127.0.0.1]) by mail83-db8 (MessageSwitch) id 1388449587833252_13269; Tue, 31 Dec 2013 00:26:27 +0000 (UTC) Received: from DB8EHSMHS010.bigfish.com (unknown [10.174.8.242]) by mail83-db8.bigfish.com (Postfix) with ESMTP id B6A4EC40049; Tue, 31 Dec 2013 00:26:27 +0000 (UTC) Received: from sj-itexedge01.altera.priv.altera.com (66.35.236.231) by DB8EHSMHS010.bigfish.com (10.174.4.20) with Microsoft SMTP Server (TLS) id 14.16.227.3; Tue, 31 Dec 2013 00:26:27 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by sj-itexedge01.altera.priv.altera.com (66.35.236.231) with Microsoft SMTP Server id 8.3.298.1; Mon, 30 Dec 2013 16:17:42 -0800 Received: from clsee-VirtualBox.altera.com (tx-clsee-530.altera.priv.altera.com [137.57.188.101]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id rBV0QIs7028779; Mon, 30 Dec 2013 16:26:24 -0800 (PST) From: Chin Liang See To: ZY - u-boot Date: Mon, 30 Dec 2013 18:26:14 -0600 Message-ID: <1388449574-6818-1-git-send-email-clsee@altera.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: Pantelis@theia.denx.de, Antoniou , Chin Liang See , Jaehoon Chung , Rajeshwari Shinde Subject: [U-Boot] [PATCH v3] socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGA X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de To add the DesignWare MMC driver support for Altera SOCFPGA. It required information such as clocks and bus width from platform specific files (SOCFPGA handoff files) Signed-off-by: Chin Liang See Cc: Rajeshwari Shinde Cc: Jaehoon Chung Cc: Pantelis Antoniou Cc: Wolfgang Denk Acked-by: Pantelis Antoniou --- Changes for v3 - Used structure instead macro for the register access - Made drvsel and smpsel configurable - Used better macro names - Added a documentation on macro used to enable the driver Changes for v2 - Adding u-boot-mmc maintainer --- arch/arm/include/asm/arch-socfpga/dwmmc.h | 12 ++++ arch/arm/include/asm/arch-socfpga/system_manager.h | 65 +++++++++++++++++++ doc/README.socfpga | 53 +++++++++++++++ drivers/mmc/Makefile | 1 + drivers/mmc/socfpga_dw_mmc.c | 68 ++++++++++++++++++++ 5 files changed, 199 insertions(+) create mode 100644 arch/arm/include/asm/arch-socfpga/dwmmc.h create mode 100644 doc/README.socfpga create mode 100644 drivers/mmc/socfpga_dw_mmc.c diff --git a/arch/arm/include/asm/arch-socfpga/dwmmc.h b/arch/arm/include/asm/arch-socfpga/dwmmc.h new file mode 100644 index 0000000..945eb64 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/dwmmc.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SOCFPGA_DWMMC_H_ +#define _SOCFPGA_DWMMC_H_ + +extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index); + +#endif /* _SOCFPGA_SDMMC_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h index d965d25..838d210 100644 --- a/arch/arm/include/asm/arch-socfpga/system_manager.h +++ b/arch/arm/include/asm/arch-socfpga/system_manager.h @@ -19,4 +19,69 @@ extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM]; #define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400) +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) + +struct socfpga_system_manager { + u32 siliconid1; + u32 siliconid2; + u32 _pad_0x8_0xf[2]; + u32 wddbg; + u32 bootinfo; + u32 hpsinfo; + u32 parityinj; + u32 fpgaintfgrp_gbl; + u32 fpgaintfgrp_indiv; + u32 fpgaintfgrp_module; + u32 _pad_0x2c_0x2f; + u32 scanmgrgrp_ctrl; + u32 _pad_0x34_0x3f[3]; + u32 frzctrl_vioctrl; + u32 _pad_0x44_0x4f[3]; + u32 frzctrl_hioctrl; + u32 frzctrl_src; + u32 frzctrl_hwctrl; + u32 _pad_0x5c_0x5f; + u32 emacgrp_ctrl; + u32 emacgrp_l3master; + u32 _pad_0x68_0x6f[2]; + u32 dmagrp_ctrl; + u32 dmagrp_persecurity; + u32 _pad_0x78_0x7f[2]; + u32 iswgrp_handoff[8]; + u32 _pad_0xa0_0xbf[8]; + u32 romcodegrp_ctrl; + u32 romcodegrp_cpu1startaddr; + u32 romcodegrp_initswstate; + u32 romcodegrp_initswlastld; + u32 romcodegrp_bootromswstate; + u32 __pad_0xd4_0xdf[3]; + u32 romcodegrp_warmramgrp_enable; + u32 romcodegrp_warmramgrp_datastart; + u32 romcodegrp_warmramgrp_length; + u32 romcodegrp_warmramgrp_execution; + u32 romcodegrp_warmramgrp_crc; + u32 __pad_0xf4_0xff[3]; + u32 romhwgrp_ctrl; + u32 _pad_0x104_0x107; + u32 sdmmcgrp_ctrl; + u32 sdmmcgrp_l3master; + u32 nandgrp_bootstrap; + u32 nandgrp_l3master; + u32 usbgrp_l3master; + u32 _pad_0x11c_0x13f[9]; + u32 eccgrp_l2; + u32 eccgrp_ocram; + u32 eccgrp_usb0; + u32 eccgrp_usb1; + u32 eccgrp_emac0; + u32 eccgrp_emac1; + u32 eccgrp_dma; + u32 eccgrp_can0; + u32 eccgrp_can1; + u32 eccgrp_nand; + u32 eccgrp_qspi; + u32 eccgrp_sdmmc; +}; + #endif /* _SYSTEM_MANAGER_H_ */ diff --git a/doc/README.socfpga b/doc/README.socfpga new file mode 100644 index 0000000..cfcbbfe --- /dev/null +++ b/doc/README.socfpga @@ -0,0 +1,53 @@ + +-------------------------------------------- +SOCFPGA Documentation for U-Boot and SPL +-------------------------------------------- + +This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore +based SOCFPGA. To know more about the hardware itself, please refer to +www.altera.com. + + +-------------------------------------------- +socfpga_dw_mmc +-------------------------------------------- +Here are macro and detailed configuration required to enable DesignWare SDMMC +controller support within SOCFPGA + +#define CONFIG_MMC +-> To enable the SD MMC framework support + +#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS) +-> The base address of CSR register for DesignWare SDMMC controller + +#define CONFIG_GENERIC_MMC +-> Enable the generic MMC driver + +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 +-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM + +#define CONFIG_DWMMC +-> Enable the common DesignWare SDMMC controller framework + +#define CONFIG_SOCFPGA_DWMMC +-> Enable the SOCFPGA specific driver for DesignWare SDMMC controller + +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 +-> The FIFO depth for SOCFPGA DesignWare SDMMC controller + +#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 +-> Phase-shifted clock of sdmmc_clk for controller to drive command and data to +the card to meet hold time requirements. SD clock is running at 50MHz and +drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time +is 135 / 360 * 20ns = 7.5ns. + +#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 +-> Phase-shifted clock of sdmmc_clk used to sample the command and data from +the card + +#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4 +-> Bus width of data line which either 1, 4 or 8 and based on board routing. + +#define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000 +-> The clock rate to controller. Do note the controller have a wrapper which +divide the clock from PLL by 4. diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 1ed26ca..e793ed9 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o obj-$(CONFIG_DWMMC) += dw_mmc.o obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o +obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o else diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c new file mode 100644 index 0000000..bc53a5d --- /dev/null +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static const struct socfpga_clock_manager *clock_manager_base = + (void *)SOCFPGA_CLKMGR_ADDRESS; +static const struct socfpga_system_manager *system_manager_base = + (void *)SOCFPGA_SYSMGR_ADDRESS; + +static char *SOCFPGA_NAME = "SOCFPGA DWMMC"; + +static void socfpga_dwmci_clksel(struct dwmci_host *host) +{ + unsigned int drvsel; + unsigned int smplsel; + + /* Disable SDMMC clock. */ + clrbits_le32(&clock_manager_base->per_pll_en, + CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); + + /* Configures drv_sel and smpl_sel */ + drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL; + smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL; + + debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel); + writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel), + &system_manager_base->sdmmcgrp_ctrl); + + debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, + readl(&system_manager_base->sdmmcgrp_ctrl)); + + /* Enable SDMMC clock */ + setbits_le32(&clock_manager_base->per_pll_en, + CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); +} + +int socfpga_dwmmc_init(u32 regbase, int bus_width, int index) +{ + struct dwmci_host *host = NULL; + host = calloc(sizeof(struct dwmci_host), 1); + if (!host) { + printf("dwmci_host calloc fail!\n"); + return -1; + } + + host->name = SOCFPGA_NAME; + host->ioaddr = (void *)regbase; + host->buswidth = bus_width; + host->clksel = socfpga_dwmci_clksel; + host->dev_index = index; + /* fixed clock divide by 4 which due to the SDMMC wrapper */ + host->bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ; + host->fifoth_val = MSIZE(0x2) | + RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) | + TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2); + + return add_dwmci(host, host->bus_hz, 400000); +} +