From patchwork Thu Dec 26 16:51:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 305290 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B86792C0040 for ; Fri, 27 Dec 2013 03:52:45 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0A1574AA20; Thu, 26 Dec 2013 17:52:36 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tXRCPweqUK2g; Thu, 26 Dec 2013 17:52:35 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 79C714AA28; Thu, 26 Dec 2013 17:52:27 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3CF1E4A072 for ; Thu, 26 Dec 2013 17:52:14 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Wzah8cco7JMS for ; Thu, 26 Dec 2013 17:52:09 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 BL_NJABL=SKIP(-1.5) (only DNSBL check requested) Received: from mail-qe0-f50.google.com (mail-qe0-f50.google.com [209.85.128.50]) by theia.denx.de (Postfix) with ESMTPS id 060A24A061 for ; Thu, 26 Dec 2013 17:52:07 +0100 (CET) Received: by mail-qe0-f50.google.com with SMTP id 1so8115973qec.37 for ; Thu, 26 Dec 2013 08:52:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sITNTN1o6fVQmCv44Sz8Z0IGfqJyZP90NhxG0dJODPU=; b=HbfovFJvre3reHPEvoJaMhDDaiFEJGdZv8xn9KZLkrTlnu9WnOmMJDxV+5Gb6wUhnP 5EhXN1kJaZfSDW5IYlEt54sE57AoX8Wvn4yGyqCA5geC5fKxSxPDJaNMk/v4VZ4Queuw lhaROKSLNhXK/seO2ayss1CsanyuyYz+c7vLWqIlZMX2bP22odpql2hYNv/LlmbIkIIV DVSqy1V+ovoRdJ+mCOtNfYRNmijT0/0jeG1vV5OKhRC62LdMRBEWhw9CWRw3UjkmSmwi r8BhufKauLuY8610ZicF1V2OBXg3pOtrJwe5+NeDrEvLNBvXcDuyAu4bzAz/no+Vuk6P rhpg== X-Received: by 10.224.43.72 with SMTP id v8mr72382048qae.52.1388076726469; Thu, 26 Dec 2013 08:52:06 -0800 (PST) Received: from localhost.localdomain ([186.207.93.139]) by mx.google.com with ESMTPSA id r9sm38717831qey.19.2013.12.26.08.52.03 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 26 Dec 2013 08:52:05 -0800 (PST) From: Fabio Estevam To: sbabic@denx.de Date: Thu, 26 Dec 2013 14:51:35 -0200 Message-Id: <1388076695-28174-6-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1388076695-28174-1-git-send-email-festevam@gmail.com> References: <1388076695-28174-1-git-send-email-festevam@gmail.com> Cc: Fabio Estevam , u-boot@lists.denx.de, RA5478@freescale.com, b20788@freescale.com Subject: [U-Boot] [PATCH v2 6/6] mx6: soc: Disable VDDPU regulator X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Fabio Estevam As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power. Signed-off-by: Anson Huang Signed-off-by: Jason Liu Signed-off-by: Fabio Estevam --- Changes since v1: - Disable vddpu the same way as in kernel arch/arm/cpu/armv7/mx6/soc.c | 41 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/crm_regs.h | 1 + arch/arm/include/asm/arch-mx6/imx-regs.h | 23 ++++++++++++++++++ 3 files changed, 65 insertions(+) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 0208cba..b944edd 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -19,6 +19,8 @@ #include #include +#define VDDPU_MASK (0x1f << 9) + enum ldo_reg { LDO_ARM, LDO_SOC, @@ -177,11 +179,50 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog2->wmcr); } +static void imx_set_vddpu_power_down(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR; + + u32 reg; + + /* + * Disable the brown out detection since we are going to be + * disabling the LDO. + */ + reg = readl(&anatop->ana_misc2); + reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN; + writel(reg, &anatop->ana_misc2); + + /* need to power down xPU in GPC before turning off PU LDO */ + reg = readl(&gpc->gpu_ctrl); + writel(reg | 0x1, &gpc->gpu_ctrl); + + reg = readl(&gpc->ctrl); + writel(reg | 0x1, &gpc->ctrl); + while (readl(&gpc->ctrl) & 0x1) + ; + + /* Mask the ANATOP brown out interrupt in the GPC. */ + reg = readl(&gpc->imr4); + reg |= 0x80000000; + writel(reg, &gpc->imr4); + + /* disable VDDPU */ + writel(VDDPU_MASK, &anatop->reg_core_clr); + + /* Clear the BO interrupt in the ANATOP. */ + reg = readl(&anatop->ana_misc1); + reg |= 0x80000000; + writel(reg, &anatop->ana_misc1); +} + int arch_cpu_init(void) { init_aips(); imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ + imx_set_vddpu_power_down(); #ifdef CONFIG_APBH_DMA /* Start APBH DMA */ diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 7202073..aede126 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -890,4 +890,5 @@ struct mxc_ccm_reg { #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) +#define ANADIG_ANA_MISC2_REG1_BO_EN (1 << 13) #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 7ef7152..fb0c4c7 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -659,5 +659,28 @@ struct wdog_regs { u16 wmcr; /* Miscellaneous Control */ }; +struct gpc_regs { + u32 ctrl; /* 0x000 */ + u32 pgr; /* 0x004 */ + u32 imr1; /* 0x008 */ + u32 imr2; /* 0x00c */ + u32 imr3; /* 0x010 */ + u32 imr4; /* 0x014 */ + u32 isr1; /* 0x018 */ + u32 isr2; /* 0x01c */ + u32 isr3; /* 0x020 */ + u32 isr4; /* 0x024 */ + u32 reserved1[0x86]; + u32 gpu_ctrl; /* 0x260 */ + u32 gpu_pupscr; /* 0x264 */ + u32 gpu_pdnscr; /* 0x268 */ + u32 gpu_sr; /* 0x26c */ + u32 reserved2[0xc]; + u32 cpu_ctrl; /* 0x2a0 */ + u32 cpu_pupscr; /* 0x2a4 */ + u32 cpu_pdnscr; /* 0x2a8 */ + u32 cpu_sr; /* 0x2ac */ +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */