From patchwork Wed Dec 18 17:16:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin Liang See X-Patchwork-Id: 302985 X-Patchwork-Delegate: panto@antoniou-consulting.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4BA9A2C007B for ; Thu, 19 Dec 2013 04:17:06 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E3CED4A99C; Wed, 18 Dec 2013 18:17:04 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3RvA+CBbDFKQ; Wed, 18 Dec 2013 18:17:04 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 73A194A9B3; Wed, 18 Dec 2013 18:17:01 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5FB084A22C for ; Wed, 18 Dec 2013 18:16:56 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QxQ4EAA1N9RZ for ; Wed, 18 Dec 2013 18:16:52 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 BL_NJABL=ERR(-1.5) (only DNSBL check requested) Received: from co1outboundpool.messaging.microsoft.com (co1ehsobe002.messaging.microsoft.com [216.32.180.185]) by theia.denx.de (Postfix) with ESMTPS id 93A874A98B for ; Wed, 18 Dec 2013 18:16:38 +0100 (CET) Received: from mail219-co1-R.bigfish.com (10.243.78.245) by CO1EHSOBE039.bigfish.com (10.243.66.104) with Microsoft SMTP Server id 14.1.225.22; Wed, 18 Dec 2013 17:16:36 +0000 Received: from mail219-co1 (localhost [127.0.0.1]) by mail219-co1-R.bigfish.com (Postfix) with ESMTP id 355AF1007F0; Wed, 18 Dec 2013 17:16:36 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.231; KIP:(null); UIP:(null); IPV:NLI; H:sj-itexedge01.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2fh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah224fh1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e1dh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received-SPF: pass (mail219-co1: domain of altera.com designates 66.35.236.231 as permitted sender) client-ip=66.35.236.231; envelope-from=clsee@altera.com; helo=sj-itexedge01.altera.priv.altera.com ; v.altera.com ; Received: from mail219-co1 (localhost.localdomain [127.0.0.1]) by mail219-co1 (MessageSwitch) id 1387386994876564_13928; Wed, 18 Dec 2013 17:16:34 +0000 (UTC) Received: from CO1EHSMHS002.bigfish.com (unknown [10.243.78.243]) by mail219-co1.bigfish.com (Postfix) with ESMTP id D2AFB4C0047; Wed, 18 Dec 2013 17:16:34 +0000 (UTC) Received: from sj-itexedge01.altera.priv.altera.com (66.35.236.231) by CO1EHSMHS002.bigfish.com (10.243.66.12) with Microsoft SMTP Server (TLS) id 14.16.227.3; Wed, 18 Dec 2013 17:16:34 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by sj-itexedge01.altera.priv.altera.com (66.35.236.231) with Microsoft SMTP Server id 8.3.298.1; Wed, 18 Dec 2013 09:08:00 -0800 Received: from clsee-VirtualBox.altera.com (tx-clsee-530.altera.priv.altera.com [137.57.188.152]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id rBIHGSq6008897; Wed, 18 Dec 2013 09:16:32 -0800 (PST) From: Chin Liang See To: ZY - u-boot Date: Wed, 18 Dec 2013 11:16:27 -0600 Message-ID: <1387386987-3581-1-git-send-email-clsee@altera.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: Pantelis Antoniou , Chin Liang See , Jaehoon Chung , Fleming , Rajeshwari Shinde , Andy@theia.denx.de Subject: [U-Boot] [PATCH v2] socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGA X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de To add the DesignWare MMC driver support for Altera SOCFPGA. It required information such as clocks and bus width from platform specific files (SOCFPGA handoff files) Signed-off-by: Chin Liang See Cc: Rajeshwari Shinde Cc: Jaehoon Chung Cc: Andy Fleming Cc: Pantelis Antoniou --- Changes for v2 - Adding u-boot-mmc maintainer --- arch/arm/include/asm/arch-socfpga/dwmmc.h | 12 +++++ drivers/mmc/Makefile | 1 + drivers/mmc/socfpga_dw_mmc.c | 72 +++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100755 arch/arm/include/asm/arch-socfpga/dwmmc.h create mode 100755 drivers/mmc/socfpga_dw_mmc.c diff --git a/arch/arm/include/asm/arch-socfpga/dwmmc.h b/arch/arm/include/asm/arch-socfpga/dwmmc.h new file mode 100755 index 0000000..945eb64 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/dwmmc.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SOCFPGA_DWMMC_H_ +#define _SOCFPGA_DWMMC_H_ + +extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index); + +#endif /* _SOCFPGA_SDMMC_H_ */ diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 1ed26ca..e793ed9 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o obj-$(CONFIG_DWMMC) += dw_mmc.o obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o +obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o else diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c new file mode 100755 index 0000000..554f51b --- /dev/null +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define CLKMGR_PERPLLGRP_EN_REG (SOCFPGA_CLKMGR_ADDRESS + 0xA0) +#define CLKMGR_SDMMC_CLK_ENABLE (1 << 8) +#define SYSMGR_SDMMCGRP_CTRL_REG (SOCFPGA_SYSMGR_ADDRESS + 0x108) +#define SYSMGR_SDMMC_CTRL_GET_DRVSEL(x) (((x) >> 0) & 0x7) +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) + +static char *SOCFPGA_NAME = "SOCFPGA DWMMC"; + +static void socfpga_dwmci_clksel(struct dwmci_host *host) +{ + unsigned int en; + unsigned int drvsel; + unsigned int smplsel; + + /* Disable SDMMC clock. */ + en = readl(CLKMGR_PERPLLGRP_EN_REG); + en &= ~CLKMGR_SDMMC_CLK_ENABLE; + writel(en, CLKMGR_PERPLLGRP_EN_REG); + + /* Configures drv_sel and smpl_sel */ + drvsel = 3; + smplsel = 0; + + debug("%s: drvsel %d smplsel %d\n", __FUNCTION__, drvsel, smplsel); + writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel), + SYSMGR_SDMMCGRP_CTRL_REG); + + debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __FUNCTION__, + readl(SYSMGR_SDMMCGRP_CTRL_REG)); + /* Enable SDMMC clock */ + en = readl(CLKMGR_PERPLLGRP_EN_REG); + en |= CLKMGR_SDMMC_CLK_ENABLE; + writel(en, CLKMGR_PERPLLGRP_EN_REG); +} + +int socfpga_dwmmc_init(u32 regbase, int bus_width, int index) +{ + struct dwmci_host *host = NULL; + host = calloc(sizeof(struct dwmci_host), 1); + if (!host) { + printf("dwmci_host calloc fail!\n"); + return 1; + } + + host->name = SOCFPGA_NAME; + host->ioaddr = (void *)regbase; + host->buswidth = bus_width; + host->clksel = socfpga_dwmci_clksel; + host->dev_index = index; + /* fixed clock divide by 4 which due to the SDMMC wrapper */ + host->bus_hz = CONFIG_DWMMC_BUS_HZ; + host->fifoth_val = MSIZE(0x2) | + RX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2 - 1) | + TX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2); + + add_dwmci(host, host->bus_hz, 400000); + + return 0; +} +