| Message ID | 1386246261-29456-1-git-send-email-pekon@ti.com |
|---|---|
| State | Accepted |
| Delegated to: | Scott Wood |
| Headers | show |
On 05.12.2013 13:24, Pekon Gupta wrote: > As per OMAP3530 TRM referenced below [1] > > For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme > - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device > - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device > > Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is: > *for x8 NAND Device* > +--------+---------+---------+---------+---------+---------+---------+ > | xxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ... > +--------+---------+---------+---------+---------+---------+---------+ > > *for x16 NAND Device* > +--------+--------+---------+---------+---------+---------+---------+---------+ > | xxxxx | xxxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | > +--------+--------+---------+---------+---------+---------+---------+---------+ > > This patch fixes ecc-layout *only* for HAM1, as required by ROM-code > For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices. > > [1] OMAP3530: http://www.ti.com/product/omap3530 > TRM: http://www.ti.com/litv/pdf/spruf98x > Chapter-25: Initialization Sub-topic: Memory Booting > Section: 25.4.7.4 NAND > Figure 25-19. ECC Locations in NAND Spare Areas > > Reported-by: Stefan Roese <sr@denx.de> > Signed-off-by: Pekon Gupta <pekon@ti.com> This fixes the problem I reported. Tested again on x8 and x16 NAND OMAP3530 targets. Thanks Pekon! Tested-by: Stefan Roese <sr@denx.de> Thanks, Stefan
On Thu, Dec 05, 2013 at 05:54:21PM +0530, pekon gupta wrote: > As per OMAP3530 TRM referenced below [1] > > For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme > - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device > - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device > > Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is: > *for x8 NAND Device* > +--------+---------+---------+---------+---------+---------+---------+ > | xxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ... > +--------+---------+---------+---------+---------+---------+---------+ > > *for x16 NAND Device* > +--------+--------+---------+---------+---------+---------+---------+---------+ > | xxxxx | xxxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | > +--------+--------+---------+---------+---------+---------+---------+---------+ > > This patch fixes ecc-layout *only* for HAM1, as required by ROM-code > For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices. > > [1] OMAP3530: http://www.ti.com/product/omap3530 > TRM: http://www.ti.com/litv/pdf/spruf98x > Chapter-25: Initialization Sub-topic: Memory Booting > Section: 25.4.7.4 NAND > Figure 25-19. ECC Locations in NAND Spare Areas > > Reported-by: Stefan Roese <sr@denx.de> > Signed-off-by: Pekon Gupta <pekon@ti.com> > Tested-by: Stefan Roese <sr@denx.de> > > --- > drivers/mtd/nand/omap_gpmc.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) Applied to u-boot-nand-flash.git -Scott
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 887b38b..fae00be 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -626,8 +626,12 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.calculate = omap_calculate_ecc; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps; - for (i = 0; i < ecclayout->eccbytes; i++) - ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH; + for (i = 0; i < ecclayout->eccbytes; i++) { + if (nand->options & NAND_BUSWIDTH_16) + ecclayout->eccpos[i] = i + 2; + else + ecclayout->eccpos[i] = i + 1; + } ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - BADBLOCK_MARKER_LENGTH;
As per OMAP3530 TRM referenced below [1] For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is: *for x8 NAND Device* +--------+---------+---------+---------+---------+---------+---------+ | xxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ... +--------+---------+---------+---------+---------+---------+---------+ *for x16 NAND Device* +--------+--------+---------+---------+---------+---------+---------+---------+ | xxxxx | xxxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | +--------+--------+---------+---------+---------+---------+---------+---------+ This patch fixes ecc-layout *only* for HAM1, as required by ROM-code For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices. [1] OMAP3530: http://www.ti.com/product/omap3530 TRM: http://www.ti.com/litv/pdf/spruf98x Chapter-25: Initialization Sub-topic: Memory Booting Section: 25.4.7.4 NAND Figure 25-19. ECC Locations in NAND Spare Areas Reported-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> --- drivers/mtd/nand/omap_gpmc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)