From patchwork Thu Nov 21 06:18:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 292986 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id EBFBA2C0196 for ; Thu, 21 Nov 2013 17:19:04 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 44A3A4A852; Thu, 21 Nov 2013 07:19:02 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Yzls-xQUZk3y; Thu, 21 Nov 2013 07:19:02 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A938E4A813; Thu, 21 Nov 2013 07:18:48 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B76944A81A for ; Thu, 21 Nov 2013 07:18:40 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LdQju9yzbvIg for ; Thu, 21 Nov 2013 07:18:34 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by theia.denx.de (Postfix) with ESMTPS id 6D25D4A811 for ; Thu, 21 Nov 2013 07:18:28 +0100 (CET) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id rAL6IQlP015635; Thu, 21 Nov 2013 00:18:26 -0600 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id rAL6IQkD023619; Thu, 21 Nov 2013 00:18:26 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Thu, 21 Nov 2013 00:18:25 -0600 Received: from a0131933lt.apr.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id rAL6IKDp021590; Thu, 21 Nov 2013 00:18:23 -0600 From: Lokesh Vutla To: Date: Thu, 21 Nov 2013 11:48:06 +0530 Message-ID: <1385014699-7257-2-git-send-email-lokeshvutla@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1385014699-7257-1-git-send-email-lokeshvutla@ti.com> References: <1385014699-7257-1-git-send-email-lokeshvutla@ti.com> MIME-Version: 1.0 Cc: rnayak@ti.com, nsekhar@ti.com, trini@ti.com Subject: [U-Boot] [PATCH V2 01/14] ARM: AM43xx: Update the base addresses of modules X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de PRCM, timer base addresses and offsets are different from AM33xx. Updating the same. Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/arch-am33xx/cpu.h | 17 +++++++++++------ arch/arm/include/asm/arch-am33xx/hardware.h | 7 ------- arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 2 ++ arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 2 ++ arch/arm/include/asm/arch-am33xx/hardware_ti814x.h | 2 ++ arch/arm/include/asm/arch-am33xx/hardware_ti816x.h | 2 ++ 6 files changed, 19 insertions(+), 13 deletions(-) diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 05752ce..19b8469 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -237,6 +237,14 @@ struct cm_perpll { unsigned int cpswclkstctrl; /* offset 0x144 */ unsigned int lcdcclkstctrl; /* offset 0x148 */ }; + +/* Encapsulating Display pll registers */ +struct cm_dpll { + unsigned int resv1[2]; + unsigned int clktimer2clk; /* offset 0x08 */ + unsigned int resv2[10]; + unsigned int clklcdcpixelclk; /* offset 0x34 */ +}; #else /* Encapsulating core pll registers */ struct cm_wkuppll { @@ -392,15 +400,12 @@ struct cm_perpll { unsigned int resv40[7]; unsigned int cpgmac0clkctrl; /* offset 0xB20 */ }; -#endif /* CONFIG_AM43XX */ -/* Encapsulating Display pll registers */ struct cm_dpll { - unsigned int resv1[2]; - unsigned int clktimer2clk; /* offset 0x08 */ - unsigned int resv2[10]; - unsigned int clklcdcpixelclk; /* offset 0x34 */ + unsigned int resv1; + unsigned int clktimer2clk; /* offset 0x04 */ }; +#endif /* CONFIG_AM43XX */ /* Control Module RTC registers */ struct cm_rtc { diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index ee5fce0..dd950e5 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -48,13 +48,6 @@ #define EMIF4_0_CFG_BASE 0x4C000000 #define EMIF4_1_CFG_BASE 0x4D000000 -/* PLL related registers */ -#define CM_DPLL 0x44E00500 -#define CM_DEVICE 0x44E00700 -#define CM_RTC 0x44E00800 -#define CM_CEFUSE 0x44E00A00 -#define PRM_DEVICE 0x44E00F00 - /* DDR Base address */ #define DDR_CTRL_ADDR 0x44E10E04 #define DDR_CONTROL_BASE_ADDR 0x44E11404 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index e4231c8..c67a080 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -30,6 +30,8 @@ #define PRCM_BASE 0x44E00000 #define CM_PER 0x44E00000 #define CM_WKUP 0x44E00400 +#define CM_DPLL 0x44E00500 +#define CM_RTC 0x44E00800 #define PRM_RSTCTRL (PRCM_BASE + 0x0F00) #define PRM_RSTST (PRM_RSTCTRL + 8) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 3b665e6..64f9c99 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -30,6 +30,8 @@ #define PRCM_BASE 0x44DF0000 #define CM_WKUP 0x44DF2800 #define CM_PER 0x44DF8800 +#define CM_DPLL 0x44DF4200 +#define CM_RTC 0x44df8500 #define PRM_RSTCTRL (PRCM_BASE + 0x4000) #define PRM_RSTST (PRM_RSTCTRL + 4) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h index 4509a23..9080b6f 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -27,6 +27,8 @@ #define PRCM_BASE 0x48180000 #define CM_PER 0x44E00000 #define CM_WKUP 0x44E00400 +#define CM_DPLL 0x44E00500 +#define CM_RTC 0x44E00800 #define PRM_RSTCTRL (PRCM_BASE + 0x00A0) #define PRM_RSTST (PRM_RSTCTRL + 8) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h index 3c68064..0f6a016 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h @@ -34,6 +34,8 @@ /* PRCM Base Address */ #define PRCM_BASE 0x48180000 +#define CM_DPLL 0x44E00500 +#define CM_RTC 0x44E00800 #define PRM_RSTCTRL (PRCM_BASE + 0x00A0) #define PRM_RSTST (PRM_RSTCTRL + 8)