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Tue, 12 Nov 2013 21:07:32 +0900 (KST) X-AuditID: cbfee691-b7f866d000001b8c-a9-52821a043188 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id F0.14.09687.40A12825; Tue, 12 Nov 2013 21:07:32 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MW500C3ZGC8LF40@mmp2.samsung.com>; Tue, 12 Nov 2013 21:07:32 +0900 (KST) From: Ajay Kumar To: u-boot@lists.denx.de, mk7.kang@samsung.com, dh09.lee@samsung.com Date: Tue, 12 Nov 2013 17:57:16 +0530 Message-id: <1384259240-7829-4-git-send-email-ajaykumar.rs@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1384259240-7829-1-git-send-email-ajaykumar.rs@samsung.com> References: <1384259240-7829-1-git-send-email-ajaykumar.rs@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLLMWRmVeSWpSXmKPExsWyRsSkRpdFqinIYEqbicX183YWHUdaGC1+ HvvObPF2bye7A4vHgk2lHmfv7GD06NuyijGAOYrLJiU1J7MstUjfLoErY835DvaCDQoV6xbN YWtgnCnVxcjJISFgIvFtw2wWCFtM4sK99WxdjFwcQgJLGSVuzFnOCFO0a/dCZojEdEaJ3z+m M0E4s5kkVu2bzwxSxSagLbFt+k2wUSICLhJrZvaAdTMLCEksmPydHcQWFoiX2H3hBlicRUBV 4lT7XLA4r4C7xMN//5kgtilKdD+bwAZicwp4SJz8dAEsLgRUs/3YJkaQxRICn9kkTi6cyg4x SEDi2+RDQIs5gBKyEpsOMEPMkZQ4uOIGywRG4QWMDKsYRVMLkguKk9KLTPWKE3OLS/PS9ZLz czcxAoP29L9nE3cw3j9gfYgxGWjcRGYp0eR8YNDnlcQbGpsZWZiamBobmVuakSasJM6b/igp SEggPbEkNTs1tSC1KL6oNCe1+BAjEwenVANjXc4Eaf6vpvs12JZxxvlqfV29jTv0Z/15i/lb Y+Zr3XqUVz7VkOF80NItGbKzTIUUL3wNFxD4Its1mc0lQZ9tl6f3vRhF2eA3RT9/zTq7t+eh 1oOd701nGGU6yzlmLz6+qu128OxXNjLuEyc7vai+n7va8cqfuHkrWDsat/worKhLE6w3OX1R iaU4I9FQi7moOBEAMHRA6XACAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFIsWRmVeSWpSXmKPExsVy+t9jQV0WqaYgg1k3tC2un7ez6DjSwmjx 89h3Zou3ezvZHVg8Fmwq9Th7ZwejR9+WVYwBzFENjDYZqYkpqUUKqXnJ+SmZeem2St7B8c7x pmYGhrqGlhbmSgp5ibmptkouPgG6bpk5QNuUFMoSc0qBQgGJxcVK+naYJoSGuOlawDRG6PqG BMH1GBmggYQ1jBlrznewF2xQqFi3aA5bA+NMqS5GTg4JAROJXbsXMkPYYhIX7q1n62Lk4hAS mM4o8fvHdCYIZzaTxKp988Gq2AS0JbZNv8kCYosIuEismdnDCGIzCwhJLJj8nR3EFhaIl9h9 4QZYnEVAVeJU+1ywOK+Au8TDf/+ZILYpSnQ/m8AGYnMKeEic/HQBLC4EVLP92CbGCYy8CxgZ VjGKphYkFxQnpeca6hUn5haX5qXrJefnbmIEx8QzqR2MKxssDjEKcDAq8fDu4GoMEmJNLCuu zD3EKMHBrCTCq8jcFCTEm5JYWZValB9fVJqTWnyIMRnoqonMUqLJ+cB4zSuJNzQ2MTc1NrU0 sTAxsyRNWEmc90CrdaCQQHpiSWp2ampBahHMFiYOTqkGRjP1MF2N2Xs5bskpzVINuiTff7dx qkT1aj/2kNNtsg0Fb1j+FzWHVdkwnKiT6Ds63yzZ/2Woc/S3k19tPkVG/UlablYqrjvrtv/1 1VK82hWBoaLZvRwJAiYabdUi/rYyPVvjmj+mBNYnfH4Usf+m/P1ZIWXOFd91PthOU1k7kXtu XNXcU7OUWIozEg21mIuKEwEWpLP+zQIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: sjg@google.com Subject: [U-Boot] [PATCH V3 3/7] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver. Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL. Signed-off-by: Ajay Kumar Acked-by: Simon Glass --- arch/arm/cpu/armv7/exynos/clock.c | 74 +++++++++++++++++++++++++++++-- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +- arch/arm/include/asm/arch-exynos/clk.h | 1 + 3 files changed, 73 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index b52e61a..60ca7ea 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) * VPLL_CON: MIDV [24:16] * BPLL_CON: MIDV [25:16]: Exynos5 */ - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) + if (pllreg == APLL || pllreg == MPLL || + pllreg == BPLL || pllreg == SPLL) mask = 0x3ff; else mask = 0x1ff; @@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg) r = readl(&clk->rpll_con0); k = readl(&clk->rpll_con1); break; + case SPLL: + r = readl(&clk->spll_con0); + break; default: printf("Unsupported PLL (%d)\n", pllreg); return 0; @@ -1038,6 +1042,40 @@ static unsigned long exynos5_get_lcd_clk(void) return pclk; } +static unsigned long exynos5420_get_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long pclk, sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_DISP10 + * FIMD1_SEL [4] + * 0: SCLK_RPLL + * 1: SCLK_SPLL + */ + sel = readl(&clk->src_disp10); + sel &= (1 << 4); + + if (sel) + sclk = get_pll_clk(SPLL); + else + sclk = get_pll_clk(RPLL); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + ratio = readl(&clk->div_disp10); + ratio = ratio & 0xf; + + pclk = sclk / (ratio + 1); + + return pclk; +} + void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1162,6 +1200,33 @@ void exynos5_set_lcd_clk(void) writel(cfg, &clk->div_disp1_0); } +void exynos5420_set_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned int cfg; + + /* + * CLK_SRC_DISP10 + * FIMD1_SEL [4] + * 0: SCLK_RPLL + * 1: SCLK_SPLL + */ + cfg = readl(&clk->src_disp10); + cfg &= ~(0x1 << 4); + cfg |= (0 << 4); + writel(cfg, &clk->src_disp10); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + cfg = readl(&clk->div_disp10); + cfg &= ~(0xf << 0); + cfg |= (0 << 0); + writel(cfg, &clk->div_disp10); +} + void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1657,14 +1722,17 @@ unsigned long get_lcd_clk(void) { if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); - else - return exynos5_get_lcd_clk(); + else if (proid_is_exynos5420()) + return exynos5420_get_lcd_clk(); + return exynos5_get_lcd_clk(); } void set_lcd_clk(void) { if (cpu_is_exynos4()) exynos4_set_lcd_clk(); + else if (proid_is_exynos5420()) + exynos5420_set_lcd_clk(); else exynos5_set_lcd_clk(); } diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 8e05a00..70b1c04 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -780,7 +780,7 @@ #define CLK_SRC_TOP2_VAL 0x11101000 #define CLK_SRC_TOP3_VAL 0x11111111 #define CLK_SRC_TOP4_VAL 0x11110111 -#define CLK_SRC_TOP5_VAL 0x11111100 +#define CLK_SRC_TOP5_VAL 0x11111101 #define CLK_SRC_TOP6_VAL 0x11110111 #define CLK_SRC_TOP7_VAL 0x00022200 diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index cdeef32..98faae7 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -15,6 +15,7 @@ #define VPLL 4 #define BPLL 5 #define RPLL 6 +#define SPLL 7 enum pll_src_bit { EXYNOS_SRC_MPLL = 6,