From patchwork Fri Nov 8 11:18:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 289796 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 05F0B2C00CD for ; Fri, 8 Nov 2013 22:23:45 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0CCCE4A449; Fri, 8 Nov 2013 12:23:42 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LbmSUIooNgn8; Fri, 8 Nov 2013 12:23:41 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 297A04A48A; Fri, 8 Nov 2013 12:23:36 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 353604A437 for ; Fri, 8 Nov 2013 12:23:32 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vgjCr3tor0fL for ; Fri, 8 Nov 2013 12:23:31 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from multi.imgtec.com (multi.imgtec.com [194.200.65.239]) by theia.denx.de (Postfix) with ESMTPS id 8AA9C4A449 for ; Fri, 8 Nov 2013 12:23:26 +0100 (CET) From: Paul Burton To: Date: Fri, 8 Nov 2013 11:18:57 +0000 Message-ID: <1383909539-29929-17-git-send-email-paul.burton@imgtec.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1383909539-29929-1-git-send-email-paul.burton@imgtec.com> References: <1383909539-29929-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.152.22] X-SEF-Processed: 7_3_0_01192__2013_11_08_11_23_25 Subject: [U-Boot] [PATCH 16/18] malta: setup PIIX4 interrupt route X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Without setting up the PIRQ[A:D] interrupt routes, PCI interrupts will be left disabled. Linux does not set up this routing but relies upon it having been set up by the bootloader, reading back the IRQ lines which the PIRQ[A:D] signals have been routed to. This patch routes PIRQA & PIRQB to IRQ 10, and PIRQC & PIRQD to IRQ 11. This matches the setup used by YAMON. Signed-off-by: Paul Burton --- arch/mips/include/asm/malta.h | 5 +++++ board/imgtec/malta/malta.c | 14 ++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index d8ec57c..e141eb0 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -53,4 +53,9 @@ #define MALTA_REVISION_CORID_CORE_LV 1 #define MALTA_REVISION_CORID_CORE_FPGA6 14 +#define PCI_CFG_PIIX4_PIRQRCA 0x60 +#define PCI_CFG_PIIX4_PIRQRCB 0x61 +#define PCI_CFG_PIIX4_PIRQRCC 0x62 +#define PCI_CFG_PIIX4_PIRQRCD 0x63 + #endif /* _MIPS_ASM_MALTA_H */ diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 2f92259..a1a4c01 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -169,6 +170,8 @@ struct serial_device *default_serial_console(void) void pci_init_board(void) { + pci_dev_t bdf; + switch (malta_sys_con()) { case SYSCON_GT64120: set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE)); @@ -191,4 +194,15 @@ void pci_init_board(void) 0x00000000, MALTA_MSC01_PCIIO_SIZE); break; } + + bdf = pci_find_device(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_0, 0); + if (bdf == -1) + panic("Failed to find PIIX4 PCI bridge\n"); + + /* setup PCI interrupt routing */ + pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10); + pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10); + pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11); + pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11); }