From patchwork Fri Nov 8 09:35:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edward Lin X-Patchwork-Id: 289762 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 78B912C0091 for ; Fri, 8 Nov 2013 21:40:40 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8C2374A42A; Fri, 8 Nov 2013 11:40:34 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hkuLQmHMl3-L; Fri, 8 Nov 2013 11:40:34 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0ECCF4A42B; Fri, 8 Nov 2013 11:40:17 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 540A44A3E0 for ; Fri, 8 Nov 2013 10:38:28 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id E0QtaibrpxW2 for ; Fri, 8 Nov 2013 10:38:23 +0100 (CET) X-Greylist: delayed 307 seconds by postgrey-1.27 at theia; Fri, 08 Nov 2013 10:38:15 CET X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from technexion.com (technexion.com [70.33.254.18]) by theia.denx.de (Postfix) with ESMTP id 50F814A3E5 for ; Fri, 8 Nov 2013 10:38:15 +0100 (CET) Received: from [10.20.30.57] (unknown [1.34.124.133]) by technexion.com (Postfix) with ESMTPA id D88D8DC0A4; Fri, 8 Nov 2013 17:35:17 +0800 (CST) From: Edward Lin To: u-boot@lists.denx.de In-Reply-To: <1383902865.3157.485.camel@edward-x220-laptop> References: <1383902865.3157.485.camel@edward-x220-laptop> Date: Fri, 08 Nov 2013 17:35:25 +0800 Message-ID: <1383903325.3157.493.camel@edward-x220-laptop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 X-Mailman-Approved-At: Fri, 08 Nov 2013 11:40:12 +0100 Cc: "fabio.estevam@freescale.com" , "otavio@ossystems.com.br" , Richard Hu Subject: [U-Boot] [PATCH 2/4] mx6: add structs for mmdc and ddr iomux registers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Edward Lin --- arch/arm/include/asm/arch-mx6/mx6_ddr_regs.h | 167 +++++++++++++++++++++++++++ 1 file changed, 167 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx6/mx6_ddr_regs.h diff --git a/arch/arm/include/asm/arch-mx6/mx6_ddr_regs.h b/arch/arm/include/asm/arch-mx6/mx6_ddr_regs.h new file mode 100644 index 0000000..dd5e892 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6_ddr_regs.h @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2013 TechNexion Inc. + * + * Author: Edward Lin + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_ARCH_MX6_DDR_REGS_H__ +#define __ASM_ARCH_MX6_DDR_REGS_H__ + +#define MX6_MMDC_P0_BASE 0x021b0000 +#define MX6_MMDC_P1_BASE 0x021b4000 + +/* MMDC P0/P1 Registers */ +struct mmdc_p_regs { + u32 mdctl; + u32 mdpdc; + u32 mdotc; + u32 mdcfg0; + u32 mdcfg1; + u32 mdcfg2; + u32 mdmisc; + u32 mdscr; + u32 mdref; + u32 res1[2]; + u32 mdrwd; + u32 mdor; + u32 res2[3]; + u32 mdasp; + u32 res3[240]; + u32 mapsr; + u32 res4[254]; + u32 mpzqhwctrl; + u32 res5[2]; + u32 mpwldectrl0; + u32 mpwldectrl1; + u32 res6; + u32 mpodtctrl; + u32 mprddqby0dl; + u32 mprddqby1dl; + u32 mprddqby2dl; + u32 mprddqby3dl; + u32 res7[4]; + u32 mpdgctrl0; + u32 mpdgctrl1; + u32 res8; + u32 mprddlctl; + u32 res9; + u32 mpwrdlctl; + u32 res10[25]; + u32 mpmur0; +}__attribute__((packed, aligned(4))); + +#define MX6Q_IOM_DDR_BASE 0x020e0500 +struct mx6q_iomux_ddr_regs { + u32 res1[3]; + u32 dram_sdqs5; + u32 dram_dqm5; + u32 dram_dqm4; + u32 dram_sdqs4; + u32 dram_sdqs3; + u32 dram_dqm3; + u32 dram_sdqs2; + u32 dram_dqm2; + u32 res2[16]; + u32 dram_cas; + u32 res3[2]; + u32 dram_ras; + u32 dram_reset; + u32 res4[2]; + u32 dram_sdclk_0; + u32 dram_sdba2; + u32 dram_sdcke0; + u32 dram_sdclk_1; + u32 dram_sdcke1; + u32 dram_sdodt0; + u32 dram_sdodt1; + u32 res5; + u32 dram_sdqs0; + u32 dram_dqm0; + u32 dram_sdqs1; + u32 dram_dqm1; + u32 dram_sdqs6; + u32 dram_dqm6; + u32 dram_sdqs7; + u32 dram_dqm7; +}__attribute__((packed, aligned(4))); + +#define MX6Q_IOM_GRP_BASE 0x020e0700 +struct mx6q_iomux_grp_regs { + u32 res1[18]; + u32 grp_b7ds; + u32 grp_addds; + u32 grp_ddrmode_ctl; + u32 res2; + u32 grp_ddrpke; + u32 res3[6]; + u32 grp_ddrmode; + u32 res4[3]; + u32 grp_b0ds; + u32 grp_b1ds; + u32 grp_ctlds; + u32 res5; + u32 grp_b2ds; + u32 grp_ddr_type; + u32 grp_b3ds; + u32 grp_b4ds; + u32 grp_b5ds; + u32 grp_b6ds; +}__attribute__((packed, aligned(4))); + +#define MX6DL_IOM_DDR_BASE 0x020e0400 +struct mx6dl_iomux_ddr_regs { + u32 res1[25]; + u32 dram_cas; + u32 res2[2]; + u32 dram_dqm0; + u32 dram_dqm1; + u32 dram_dqm2; + u32 dram_dqm3; + u32 dram_dqm4; + u32 dram_dqm5; + u32 dram_dqm6; + u32 dram_dqm7; + u32 dram_ras; + u32 dram_reset; + u32 res3[2]; + u32 dram_sdba2; + u32 dram_sdcke0; + u32 dram_sdcke1; + u32 dram_sdclk_0; + u32 dram_sdclk_1; + u32 dram_sdodt0; + u32 dram_sdodt1; + u32 dram_sdqs0; + u32 dram_sdqs1; + u32 dram_sdqs2; + u32 dram_sdqs3; + u32 dram_sdqs4; + u32 dram_sdqs5; + u32 dram_sdqs6; + u32 dram_sdqs7; +}__attribute__((packed, aligned(4))); + +#define MX6DL_IOM_GRP_BASE 0x020e0700 +struct mx6dl_iomux_grp_regs { + u32 res1[18]; + u32 grp_b7ds; + u32 grp_addds; + u32 grp_ddrmode_ctl; + u32 grp_ddrpke; + u32 res2[2]; + u32 grp_ddrmode; + u32 grp_b0ds; + u32 res3; + u32 grp_ctlds; + u32 grp_b1ds; + u32 grp_ddr_type; + u32 grp_b2ds; + u32 grp_b3ds; + u32 grp_b4ds; + u32 grp_b5ds; + u32 res4; + u32 grp_b6ds; +}__attribute__((packed, aligned(4))); + +#endif