From patchwork Fri Nov 8 02:06:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Haijun.Zhang" X-Patchwork-Id: 289666 X-Patchwork-Delegate: panto@antoniou-consulting.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 8DBEB2C00A9 for ; Fri, 8 Nov 2013 13:53:18 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E51F94A411; Fri, 8 Nov 2013 03:53:13 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lsB0ysRL-Vpl; Fri, 8 Nov 2013 03:53:13 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 58FA74A3DD; Fri, 8 Nov 2013 03:53:07 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 27B114A3C1 for ; Fri, 8 Nov 2013 03:51:24 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1Tum+QLF25O6 for ; Fri, 8 Nov 2013 03:51:18 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 BL_NJABL=ERR(-1.5) (only DNSBL check requested) Received: from db9outboundpool.messaging.microsoft.com (mail-db9lp0250.outbound.messaging.microsoft.com [213.199.154.250]) by theia.denx.de (Postfix) with ESMTPS id 034594A3BB for ; Fri, 8 Nov 2013 03:51:10 +0100 (CET) Received: from mail137-db9-R.bigfish.com (10.174.16.254) by DB9EHSOBE036.bigfish.com (10.174.14.99) with Microsoft SMTP Server id 14.1.225.22; Fri, 8 Nov 2013 02:51:07 +0000 Received: from mail137-db9 (localhost [127.0.0.1]) by mail137-db9-R.bigfish.com (Postfix) with ESMTP id B15542E0268; Fri, 8 Nov 2013 02:51:07 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2dh2a8h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1fe8h1ff5h2218h2216h1155h) Received: from mail137-db9 (localhost.localdomain [127.0.0.1]) by mail137-db9 (MessageSwitch) id 1383879065868623_2500; Fri, 8 Nov 2013 02:51:05 +0000 (UTC) Received: from DB9EHSMHS003.bigfish.com (unknown [10.174.16.253]) by mail137-db9.bigfish.com (Postfix) with ESMTP id CEA424800FC; Fri, 8 Nov 2013 02:51:05 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB9EHSMHS003.bigfish.com (10.174.14.13) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 8 Nov 2013 02:51:05 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.3.158.2; Fri, 8 Nov 2013 02:51:03 +0000 Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id rA82osJr031858; Thu, 7 Nov 2013 19:50:58 -0700 From: Haijun Zhang To: , , Date: Fri, 8 Nov 2013 10:06:56 +0800 Message-ID: <1383876423-2265-1-git-send-email-Haijun.Zhang@freescale.com> X-Mailer: git-send-email 1.8.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-Mailman-Approved-At: Fri, 08 Nov 2013 03:53:06 +0100 Cc: Haijun Zhang , Haijun Zhang , trini@ti.com, X.Xie@freescale.com, scottwood@freescale.com Subject: [U-Boot] [PATCH 1/7 V2] mmc: Add some usefull macro definition X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add command class define. Add mmc erase and secure erase define. Add secure erase and trim support bit define. Signed-off-by: Haijun Zhang --- changes for V2: - Changed the comment, no other change include/mmc.h | 50 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/include/mmc.h b/include/mmc.h index cb558da..08f0f3e 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -53,6 +53,7 @@ #define COMM_ERR -18 /* Communications Error */ #define TIMEOUT -19 #define IN_PROGRESS -20 /* operation is in progress */ +#define NOT_SUPPORT -21 /* Operation is not support */ #define MMC_CMD_GO_IDLE_STATE 0 #define MMC_CMD_SEND_OP_COND 1 @@ -105,6 +106,39 @@ #define OCR_VOLTAGE_MASK 0x007FFF80 #define OCR_ACCESS_MODE 0x60000000 +/* + * Card Command Classes (CCC) + * + * (0) Basic protocol functions (CMD0,1,2,3,4,7,9,10,12,13,15) + * (and for SPI, CMD58,59) + * (1) Stream read commands (CMD11) + * (2) Block read commands (CMD16,17,18) + * (3) Stream write commands (CMD20) + * (4) Block write commands (CMD16,24,25,26,27) + * (5) Ability to erase blocks (CMD32,33,34,35,36,37,38,39) + * (6) Able to write protect blocks (CMD28,29,30) + * (7) Able to lock down card (CMD16,CMD42) + * (8) Application specific (CMD55,56,57,ACMD*) + * (9) I/O mode (CMD5,39,40,52,53) + * (10) High speed switch (CMD6,34,35,36,37,50) + */ +#define CCC_BASIC (1<<0) +#define CCC_STREAM_READ (1<<1) +#define CCC_BLOCK_READ (1<<2) +#define CCC_STREAM_WRITE (1<<3) +#define CCC_BLOCK_WRITE (1<<4) +#define CCC_ERASE (1<<5) +#define CCC_WRITE_PROT (1<<6) +#define CCC_LOCK_CARD (1<<7) +#define CCC_APP_SPEC (1<<8) +#define CCC_IO_MODE (1<<9) +#define CCC_SWITCH (1<<10) + +#define MMC_ERASE_ARG 0x00000000 +#define MMC_SECURE_ERASE_ARG 0x80000000 +#define MMC_TRIM_ARG 0x00000001 +#define MMC_DISCARD_ARG 0x00000003 + #define SECURE_ERASE 0x80000000 #define MMC_STATUS_MASK (~0x0206BF7F) @@ -160,8 +194,12 @@ #define EXT_CSD_CARD_TYPE 196 /* RO */ #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ +#define EXT_CSD_REL_WR_SEC_C 222 /* RO */ +#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */ #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ #define EXT_CSD_BOOT_MULT 226 /* RO */ +#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */ +#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ /* * EXT_CSD field definitions @@ -178,6 +216,12 @@ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ +/* EXT_CSD[231] */ +#define EXT_CSD_SEC_ER_EN (1<<0) +#define EXT_CSD_SEC_BD_BLK_EN (1<<2) +#define EXT_CSD_SEC_GB_CL_EN (1<<4) +#define EXT_CSD_SEC_SANITIZE (1<<6) /* v4.5 later */ + #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) @@ -187,7 +231,6 @@ #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) - #define R1_ILLEGAL_COMMAND (1 << 22) #define R1_APP_CMD (1 << 5) @@ -268,10 +311,15 @@ struct mmc { ushort rca; char part_config; char part_num; + ushort cmdclass; uint tran_speed; uint read_bl_len; uint write_bl_len; uint erase_grp_size; + uint erase_timeout_mult; + char sec_feature_support; + uint sec_erase_mult; + uint sec_erase_timeout; u64 capacity; u64 capacity_user; u64 capacity_boot;