From patchwork Wed Oct 23 10:08:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 285612 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 2CD072C00A4 for ; Wed, 23 Oct 2013 21:15:27 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DFF9C4A201; Wed, 23 Oct 2013 12:13:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3q9VAcW7IduX; Wed, 23 Oct 2013 12:13:42 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CAB104A203; Wed, 23 Oct 2013 12:12:49 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 292334A1D8 for ; Wed, 23 Oct 2013 12:12:24 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Fid2FHjxSPzL for ; Wed, 23 Oct 2013 12:12:13 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 BL_NJABL=ERR(-1.5) (only DNSBL check requested) Received: from multi.imgtec.com (multi.imgtec.com [194.200.65.239]) by theia.denx.de (Postfix) with ESMTPS id 46BC64A19A for ; Wed, 23 Oct 2013 12:12:00 +0200 (CEST) From: Paul Burton To: Date: Wed, 23 Oct 2013 11:08:03 +0100 Message-ID: <1382522885-29524-14-git-send-email-paul.burton@imgtec.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1382522885-29524-1-git-send-email-paul.burton@imgtec.com> References: <1382522885-29524-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.152.22] X-SEF-Processed: 7_3_0_01192__2013_10_23_11_11_46 Subject: [U-Boot] [PATCH 13/15] malta: disable L2 caches X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Malta boards may be used with cores which support L2 caches, however U-boot does not yet support L2 cache for MIPS. Thus for the moment we'll disable L2 caches by setting the L2B bit in Config2. This is specific to MTI/Imagination MIPS cores which is why this is done for the Malta board rather than generically. Signed-off-by: Paul Burton --- board/malta/lowlevel_init.S | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/malta/lowlevel_init.S b/board/malta/lowlevel_init.S index 1af34f1..ae09c27 100644 --- a/board/malta/lowlevel_init.S +++ b/board/malta/lowlevel_init.S @@ -12,6 +12,7 @@ #include #include #include +#include #ifdef CONFIG_SYS_BIG_ENDIAN #define CPU_TO_GT32(_x) ((_x)) @@ -27,6 +28,12 @@ .globl lowlevel_init lowlevel_init: + /* disable any L2 cache for now */ + sync + mfc0 t0, CP0_CONFIG, 2 + ori t0, t0, 0x1 << 12 + mtc0 t0, CP0_CONFIG, 2 + /* detect the core card */ li t0, KSEG1ADDR(MALTA_REVISION) lw t0, 0(t0)