From patchwork Tue Oct 15 21:18:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Warren X-Patchwork-Id: 283789 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 71FA32C010A for ; Wed, 16 Oct 2013 08:13:59 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 391184A097; Tue, 15 Oct 2013 23:13:56 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RDe8yVQq7SMj; Tue, 15 Oct 2013 23:13:56 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AF4904A098; Tue, 15 Oct 2013 23:13:51 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E9DC24A098 for ; Tue, 15 Oct 2013 23:13:45 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3bnF7uaWyibs for ; Tue, 15 Oct 2013 23:13:39 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pb0-f52.google.com (mail-pb0-f52.google.com [209.85.160.52]) by theia.denx.de (Postfix) with ESMTPS id 8F4114A097 for ; Tue, 15 Oct 2013 23:13:32 +0200 (CEST) Received: by mail-pb0-f52.google.com with SMTP id wz12so9287300pbc.39 for ; Tue, 15 Oct 2013 14:13:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=ZLCmPWtm3oJ3rGLg3d/bD3EvtZpE5hi/rbOVdDEmopU=; b=hXdM9pXHNPcT3Rx6G93LOd7h3G0z3CyB6DwlQjn3mX8+X323USdrXj2Qahq7lfT02G J8AMmLAeQC8EexiY/WPmVfQQHKJdAubv2tzDMmwPEnuW3SbE65Jmp2TXPPPXeDle5ZvO BufXu/OpsQsWcQR51Izf+T/KNCZQBLSyTsKtrRemMaix0QLgQKMmAIzhIQDxy35eE6Qv MX3isE/KTcG2Zo6R61gsBI9iZX/JMxDUREv+VgOAxB/gCx3ydriO3Ci/XOzkX7Ubcw8K MKg2mQLQvoxqv/4GH67Jhl7v3MPhnt2frdAbBI5tWgu3MQaB4KvyR6dIoepKMxcKxZHt Y+5A== X-Received: by 10.68.219.194 with SMTP id pq2mr43386739pbc.52.1381871610423; Tue, 15 Oct 2013 14:13:30 -0700 (PDT) Received: from tom-ubuntu64.nvidia.com ([216.228.120.20]) by mx.google.com with ESMTPSA id zq10sm101426346pab.6.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 15 Oct 2013 14:13:29 -0700 (PDT) From: Tom Warren To: u-boot@lists.denx.de Date: Tue, 15 Oct 2013 14:18:36 -0700 Message-Id: <1381871916-2884-1-git-send-email-twarren@nvidia.com> X-Mailer: git-send-email 1.8.1.5 X-NVConfidentiality: public Cc: swarren@nvidia.com, jimmzhang@nvidia.com, Tom Warren , twarren.nvidia@gmail.com Subject: [U-Boot] [PATCH v2] Tegra114: SPL: Set SCLK source to CLK_M before PLLP init. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Jimmy Zhang Based on the Tegra114 TRM, SCLK (system clock) can run up to 275MHz. At POR, the default SCLK source is set to PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to 480MHz which is beyond the SCLK's upper limit. The fix is to set SCLK source to CLK_M before initializing PLLP. Tested on A02 dalmore board. Signed-off-by: Jimmy Zhang Signed-off-by: Tom Warren --- v2: - Move/clarify comments and commit msg as per StephenW - Don't remove various unrelated clock enable/reset calls arch/arm/cpu/arm720t/tegra-common/spl.c | 12 ++++++++++++ arch/arm/cpu/arm720t/tegra114/cpu.c | 20 ++++++++++++++++++-- arch/arm/cpu/tegra114-common/clock.c | 13 +++++++++++++ arch/arm/include/asm/arch-tegra/clk_rst.h | 7 +++++++ 4 files changed, 50 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c index 5171a8f..49a0544 100644 --- a/arch/arm/cpu/arm720t/tegra-common/spl.c +++ b/arch/arm/cpu/arm720t/tegra-common/spl.c @@ -17,6 +17,10 @@ #include #include "cpu.h" +__weak void set_avp_clock_to_clkm(void) +{ +} + void spl_board_init(void) { struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; @@ -24,6 +28,14 @@ void spl_board_init(void) /* enable JTAG */ writel(0xC0, &pmt->pmt_cfg_ctl); + /* + * On poweron, AVP's clock source (also called system clock, or SCLK) + * is set to PLLP_OUT0 with a frequency of 1MHz. Before initializing + * PLLP, we need to move the SCLK source to CLK_M temporarily, and then + * switch it to PLLP_OUT4 (204MHz) at a later time. + */ + set_avp_clock_to_clkm(); + board_init_uart_f(); /* Initialize periph GPIOs */ diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c index 51ecff7..8f7bce4 100644 --- a/arch/arm/cpu/arm720t/tegra114/cpu.c +++ b/arch/arm/cpu/arm720t/tegra114/cpu.c @@ -127,8 +127,8 @@ void t114_init_clocks(void) clrbits_le32(&flow->cluster_control, 1); /* - * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run - * at 108 MHz. This is glitch free as only the source is changed, no + * Switch system clock to PLLP_OUT4 (204 MHz), AVP will now run + * at 204 MHz. This is glitch free as only the source is changed, no * special precaution needed. */ val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | @@ -322,3 +322,19 @@ void start_cpu(u32 reset_vector) /* If the CPU(s) don't already have power, power 'em up */ powerup_cpus(); } + +/* Use CLK_M (crystal freq) as AVP/COP (SCLK) clock source */ +void set_avp_clock_to_clkm(void) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 val; + + val = (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | + (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | + (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | + (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | + (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); + writel(val, &clkrst->crc_sclk_brst_pol); + udelay(3); +} diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c index 5c4305a..e9a1a80 100644 --- a/arch/arm/cpu/tegra114-common/clock.c +++ b/arch/arm/cpu/tegra114-common/clock.c @@ -609,6 +609,7 @@ void clock_early_init(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; /* * PLLP output frequency set to 408Mhz @@ -653,6 +654,18 @@ void clock_early_init(void) /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */ writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); udelay(2); + + /* Set PLLP_OUT3 and 4 freqs to 102MHz and 204MHz */ + /* Assert RSTN before enable */ + reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); + + /* set divisor and reenable */ + reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) + | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS + | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) + | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); } void arch_timer_init(void) diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 074b3bc..a4c17e7 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -209,6 +209,13 @@ enum { IN_408_OUT_9_6_DIVISOR = 83, }; +#define PLLP_OUT3_RSTN_DIS (1 << 0) +#define PLLP_OUT3_RSTN_EN (0 << 0) +#define PLLP_OUT3_CLKEN (1 << 1) +#define PLLP_OUT4_RSTN_DIS (1 << 16) +#define PLLP_OUT4_RSTN_EN (0 << 16) +#define PLLP_OUT4_CLKEN (1 << 17) + /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */ #define PLLU_POWERDOWN (1 << 16) #define PLL_ENABLE_POWERDOWN (1 << 14)