From patchwork Fri Sep 20 12:40:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 276446 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id C403E2C0139 for ; Fri, 20 Sep 2013 22:51:26 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 32CF74A1A5; Fri, 20 Sep 2013 14:51:25 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YIz57vr4k0sZ; Fri, 20 Sep 2013 14:51:24 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5ED804A197; Fri, 20 Sep 2013 14:51:18 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AD51B4A197 for ; Fri, 20 Sep 2013 14:51:11 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fuItN1xsDY7t for ; Fri, 20 Sep 2013 14:50:43 +0200 (CEST) X-Greylist: delayed 490 seconds by postgrey-1.27 at theia; Fri, 20 Sep 2013 14:50:25 CEST X-policyd-weight: passed - too many local DNS-errors in dnsbl.njabl.org lookups Received: from mail-bk0-f44.google.com (unknown [209.85.214.44]) by theia.denx.de (Postfix) with ESMTPS id 922254A195 for ; Fri, 20 Sep 2013 14:50:25 +0200 (CEST) Received: by mail-bk0-f44.google.com with SMTP id mz10so170485bkb.17 for ; Fri, 20 Sep 2013 05:50:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=Vf6cBDec15p6aMyMRMvaivSiRIIBRkZmUC0W3c/HMEM=; b=Fqb7Ee3+PEKidXwGQqk/WhCisHY12X0IbUiLeobwz18Wi/+dzf9tF/AIM63xY5BbVp +tkdtQ53VQlM4e/Hx/66KVFK1Q4vfuXMy4BkdiAwdHVaUQW3occenfgFujiuzLYeYXZq 8Y66LJhtW5hxsoOG3R06qyGhfZ1Z5ZcWli21sOm4jb17fiyiz5Na0YAs+F4H5y8kMS4S lW6IrmVd3qHwN4LS2LZ56S0qmgl/cns4h4sd4w7exe4NPdmpmkZWyMqXgYwRZH7t3eFh iwQBW4vWvKmIZ6rV/hpSiqzqc5QAHpZDyi/JCKT25zR/YZLr4nxnmUSdIdNBWin5P9BK VbEA== X-Received: by 10.205.86.199 with SMTP id at7mr5312421bkc.9.1379680934041; Fri, 20 Sep 2013 05:42:14 -0700 (PDT) Received: from localhost (port-23010.pppoe.wtnet.de. [46.59.151.146]) by mx.google.com with ESMTPSA id kk2sm4557284bkb.10.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 20 Sep 2013 05:42:13 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Fri, 20 Sep 2013 14:40:59 +0200 Message-Id: <1379680859-24121-1-git-send-email-treding@nvidia.com> X-Mailer: git-send-email 1.8.4 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH] Tegra114: Fix PLLX M, N, P init settings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Jimmy Zhang The M, N and P width have been changed from Tegra30. The maximum value for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should be set accordingly. Signed-off-by: Jimmy Zhang Reviewed-by: Tom Warren Signed-off-by: Thierry Reding --- arch/arm/cpu/arm720t/tegra-common/cpu.c | 36 +++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 9294611..2c50034 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -50,7 +50,13 @@ int get_num_cpus(void) */ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { /* T20: 1 GHz */ - /* n, m, p, cpcon */ + /* + * Field Bits Width + * n 17:8 10 + * m 4:0 5 + * p 22:20 3 + */ + /* n, m, p, cpcon */ {{ 1000, 13, 0, 12}, /* OSC 13M */ { 625, 12, 0, 8}, /* OSC 19.2M */ { 1000, 12, 0, 12}, /* OSC 12M */ @@ -58,6 +64,12 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { }, /* T25: 1.2 GHz */ + /* + * Field Bits Width + * n 17:8 10 + * m 4:0 5 + * p 22:20 3 + */ {{ 923, 10, 0, 12}, { 750, 12, 0, 8}, { 600, 6, 0, 12}, @@ -65,17 +77,29 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { }, /* T30: 1.4 GHz */ + /* + * Field Bits Width + * n 17:8 10 + * m 4:0 5 + * p 22:20 3 + */ {{ 862, 8, 0, 8}, { 583, 8, 0, 4}, { 700, 6, 0, 8}, { 700, 13, 0, 8}, }, - /* T114: 1.4 GHz */ - {{ 862, 8, 0, 8}, - { 583, 8, 0, 4}, - { 696, 12, 0, 8}, - { 700, 13, 0, 8}, + /* T114: 1.9 GHz */ + /* + * Field Bits Width + * n 15:8 8 + * m 7:0 8 + * p 23:20 4 + */ + {{ 108, 1, 1, 8}, /* actual: 702.0 MHz */ + { 73, 1, 1, 4}, /* actual: 700.8 MHz */ + { 116, 1, 1, 8}, /* actual: 696.0 MHz */ + { 108, 2, 1, 8}, /* actual: 702.0 MHz */ }, };