From patchwork Tue Sep 3 08:33:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: pekon gupta X-Patchwork-Id: 272173 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 788C42C00AA for ; Tue, 3 Sep 2013 18:34:50 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 077934A06E; Tue, 3 Sep 2013 10:34:39 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IDv9VBgo2CVw; Tue, 3 Sep 2013 10:34:38 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4B9874A09D; Tue, 3 Sep 2013 10:34:27 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A47984A087 for ; Tue, 3 Sep 2013 10:34:17 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id X4jT+QVdAFIb for ; Tue, 3 Sep 2013 10:34:12 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 5A32F4A018 for ; Tue, 3 Sep 2013 10:34:05 +0200 (CEST) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r838Y0TY019998; Tue, 3 Sep 2013 03:34:00 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r838Y07K000895; Tue, 3 Sep 2013 03:34:00 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Tue, 3 Sep 2013 03:34:00 -0500 Received: from psplinux064.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id r838XpmL005289; Tue, 3 Sep 2013 03:33:58 -0500 From: Pekon Gupta To: , Date: Tue, 3 Sep 2013 14:03:49 +0530 Message-ID: <1378197229-21596-4-git-send-email-pekon@ti.com> X-Mailer: git-send-email 1.8.1 In-Reply-To: <1378197229-21596-1-git-send-email-pekon@ti.com> References: <1378197229-21596-1-git-send-email-pekon@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, balbi@ti.com Subject: [U-Boot] [PATCH v1 3/3] am335x: update README for BCH16 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Adds explanation on how to select ECC scheme. Signed-off-by: Pekon Gupta --- board/ti/am335x/README | 43 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-) diff --git a/board/ti/am335x/README b/board/ti/am335x/README index 941dfbb..05e53b1 100644 --- a/board/ti/am335x/README +++ b/board/ti/am335x/README @@ -30,12 +30,13 @@ Step-1: Building u-boot for NAND boot CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block CONFIG_SYS_NAND_ECCPOS ECC map for NAND page CONFIG_SYS_NAND_ECCSCHEME ECC scheme used by NAND - 0 - HAM1_SW - 1 - HAM1_HW + 0 - HAM1_SW (for legacy devices) + 1 - HAM1_HW (for legacy devices) 2 - BCH4_SW (unsupported) 3 - BCH4_HW (unsupported) 4 - BCH8_SW 5 - BCH8_HW + 6 - BCH16_HW Step-2: Flashing NAND via MMC/SD # select BOOTSEL to MMC/SD boot and boot from MMC/SD card @@ -63,6 +64,44 @@ Step-2: Flashing NAND via MMC/SD Step-3: Set BOOTSEL pin to select NAND boot, and POR the device. The device should boot from images flashed on NAND device. + +How to select ECC scheme ? +-------------------------- +Though higher ECC schemes have more capability to detect and correct +bit-flips, but still selection of ECC scheme is dependent on following +- hardware engines present in SoC. + Some legacy OMAP SoC do not have ELM h/w engine thus such + SoC cannot support BCHx_HW ECC schemes. +- size of OOB/Spare region + With higher ECC schemes, more OOB/Spare area is required to + store ECC. So choice of ECC scheme is limited by NAND oobsize. + +In general following expression can help: + NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES +where + NAND_OOBSIZE = number of bytes available in + OOB/spare area per NAND page. + NAND_PAGESIZE = bytes in main-area of NAND page. + ECC_BYTES = number of ECC bytes generated to + protect 512 bytes of data, which is: + 3 for HAM1_xx ecc schemes + 7 for BCH4_xx ecc schemes + 14 for BCH8_xx ecc schemes + 26 for BCH16_xx ecc schemes + + example to check for BCH16 on 2K page NAND + NAND_PAGESIZE = 2048 + NAND_OOBSIZE = 64 + 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE + Thus BCH16 cannot be supported on 2K page NAND. + + However, for 4K pagesize NAND + NAND_PAGESIZE = 4096 + NAND_OOBSIZE = 64 + ECC_BYTES = 26 + 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE + Thus BCH16 can be supported on 4K page NAND. + NOR ===