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Thu, 29 Aug 2013 19:50:46 +0900 (KST) X-AuditID: cbfee68d-b7fe86d0000077a5-bd-521f278675c8 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id A2.6F.09055.6872F125; Thu, 29 Aug 2013 19:50:46 +0900 (KST) Received: from localhost.localdomain.com ([107.108.73.95]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MSA0009BGSF2R30@mmp2.samsung.com>; Thu, 29 Aug 2013 19:50:46 +0900 (KST) From: Rajeshwari S Shinde To: u-boot@lists.denx.de Date: Thu, 29 Aug 2013 16:22:24 +0530 Message-id: <1377773544-306-1-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.11.7 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrPLMWRmVeSWpSXmKPExsWyRsSkVrdNXT7IoOGJjcWN6z/ZLB6uv8li ceNXG6tFx5EWRosph7+wWHzbso3R4u3eTnYHdo/ZDRdZPHbOusvucefaHjaPs3d2MHr0bVnF GMAaxWWTkpqTWZZapG+XwJXR8m8dc8EaiYrVF5wbGJ8KdzFyckgImEj8uHKIEcIWk7hwbz1b FyMXh5DAUkaJdb0XmGGKFm7oZ4JITGeUeLytgx3C6WKSePL/OWsXIwcHG1DVxhMJIA0iAhIS v/qvMoLUMAt0MErsmLgZbIWwgJ3Exh3nWEFsFgFViWv7H4Bt4BVwk1h85Ss7xDZFiRlLnoE1 Swi0s0scPLGbEaJBQOLb5EMsIMskBGQlNh2Auk5S4uCKGywTGAUXMDKsYhRNLUguKE5KLzLU K07MLS7NS9dLzs/dxAgM3NP/nvXuYLx9wPoQYzLQuInMUqLJ+cDAzyuJNzQ2M7IwNTE1NjK3 NCNNWEmcV63FOlBIID2xJDU7NbUgtSi+qDQntfgQIxMHp1QDo8nR+5LPtl46Etd+kmvzymVr F/49kxK4nkFfuOBt78z3vcK/DswObXT4+K0gqVtvbUHjO96KSPcjNwp/LP7W/8pzRqTMuQkn f/XJ317sLrc6Z1d15/PtTYXXTiz5Hrl8Ou/+a78ft3r8PJ+3aZvaBbNN1UF6C7K3B/duXyYy /WLbi00qn4/GBi1VYinOSDTUYi4qTgQAfMQCPXICAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrDIsWRmVeSWpSXmKPExsVy+t9jQd02dfkgg8Y+Y4sb13+yWTxcf5PF 4savNlaLjiMtjBZTDn9hsfi2ZRujxdu9newO7B6zGy6yeOycdZfd4861PWweZ+/sYPTo27KK MYA1qoHRJiM1MSW1SCE1Lzk/JTMv3VbJOzjeOd7UzMBQ19DSwlxJIS8xN9VWycUnQNctMwfo ECWFssScUqBQQGJxsZK+HaYJoSFuuhYwjRG6viFBcD1GBmggYQ1jRsu/dcwFayQqVl9wbmB8 KtzFyMkhIWAisXBDPxOELSZx4d56ti5GLg4hgemMEo+3dbBDOF1MEk/+P2ftYuTgYAPq2Hgi AaRBREBC4lf/VUaQGmaBDkaJHRM3M4IkhAXsJDbuOMcKYrMIqEpc2/+AGcTmFXCTWHzlKzvE NkWJGUueMU5g5F7AyLCKUTS1ILmgOCk911CvODG3uDQvXS85P3cTIzgunkntYFzZYHGIUYCD UYmHN+K3bJAQa2JZcWXuIUYJDmYlEd63nPJBQrwpiZVVqUX58UWlOanFhxiTgbZPZJYSTc4H xmxeSbyhsYm5qbGppYmFiZklacJK4rwHWq0DhQTSE0tSs1NTC1KLYLYwcXBKNTA6fft1LPHW v6PHr7TEVnk+Ty1UqDi65Iz5Rastb+PrD5ksW76+2FDkoo725Pi10mxHVMvFj80PU+1SeaMR 2Xtr8t/i24sTZHm33Envzm6bslflmWVx/JrCW/LMO3YGLnxr+HPJt9rJT6sz/j09+q+/59RM 4Vsn7eIN1/9Ke35go2BCfdiisrnrlFiKMxINtZiLihMBygZfXc8CAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: patches@linaro.org, jh80.chung@samsung.com, afleming@gmail.com Subject: [U-Boot] [PATCH] MMC: DWMMC: Correct the CLKDIV register value X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch corrects the divider value written to CLKDIV register. Since SDCLKIN is divided inside controller by the DIVRATIO value set in the CLKSEL register, we need to use the same output clock value to calculate the CLKDIV value. as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1) Input parameter to mmc_clk is changed to dwmci_host, since we need the same to read DWMCI_CLKSEL register. This improves the read timing values for channel 0 on SMDK5250 from 0.288sec to 0.144sec Signed-off-by: Rajeshwari S Shinde --- arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++ drivers/mmc/dw_mmc.c | 2 +- drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++-- include/dwmmc.h | 2 +- 4 files changed, 21 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index b9eca76..f1c8d8a 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -14,6 +14,10 @@ #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24) +/* CLKSEL Register */ +#define DWMCI_DIVRATIO_BIT 24 +#define DWMCI_DIVRATIO_MASK 0x7 + #ifdef CONFIG_OF_CONTROL int exynos_dwmmc_init(const void *blob); #endif diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index a82ee17..3406bdd 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -224,7 +224,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) * host->bus_hz should be set from user. */ if (host->mmc_clk) - sclk = host->mmc_clk(host->dev_index); + sclk = host->mmc_clk(host); else if (host->bus_hz) sclk = host->bus_hz; else { diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 4ef9fec..1ed4afe 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host) dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); } -unsigned int exynos_dwmci_get_clk(int dev_index) +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) { - return get_mmc_clk(dev_index); + unsigned long sclk; + int8_t clk_div; + + /* + * Since SDCLKIN is divided inside controller by the DIVRATIO + * value set in the CLKSEL register, we need to use the same output + * clock value to calculate the CLKDIV value. + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) + */ + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) + & DWMCI_DIVRATIO_MASK) + 1; + sclk = get_mmc_clk(host->dev_index); + + return sclk / clk_div; } /* diff --git a/include/dwmmc.h b/include/dwmmc.h index 08ced0b..26b53af 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -138,7 +138,7 @@ struct dwmci_host { struct mmc *mmc; void (*clksel)(struct dwmci_host *host); - unsigned int (*mmc_clk)(int dev_index); + unsigned int (*mmc_clk)(struct dwmci_host *host); }; struct dwmci_idmac {