From patchwork Tue Aug 27 11:48:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 270096 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CB13A2C00D8 for ; Tue, 27 Aug 2013 21:49:28 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 472834A062; Tue, 27 Aug 2013 13:49:25 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zNRFwOu+Qg7m; Tue, 27 Aug 2013 13:49:24 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 147004A023; Tue, 27 Aug 2013 13:49:24 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5CE824A023 for ; Tue, 27 Aug 2013 13:49:16 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RmZeBsI0PbZm for ; Tue, 27 Aug 2013 13:49:10 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mo-p05-ob.rzone.de (mo-p05-ob.rzone.de [81.169.146.180]) by theia.denx.de (Postfix) with ESMTPS id 4288E4A019 for ; Tue, 27 Aug 2013 13:49:04 +0200 (CEST) X-RZG-AUTH: :IW0NeWC7b/q2i6W/qstXb1SBUuFnrGohdvpEkce+Ub40Q/uAHDKmDv72PG5ts50= X-RZG-CLASS-ID: mo05 Received: from ubuntu-2012.fritz.box (pD958A090.dip0.t-ipconnect.de [217.88.160.144]) by smtp.strato.de (RZmta 31.46 DYNA|AUTH) with ESMTPA id 407545p7RBOkmw for ; Tue, 27 Aug 2013 13:49:00 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Date: Tue, 27 Aug 2013 13:48:56 +0200 Message-Id: <1377604136-12314-1-git-send-email-sr@denx.de> X-Mailer: git-send-email 1.8.3.4 Subject: [U-Boot] [PATCH] ppc4xx: Fix GPIO handling in lwmon5 and lcd4_lwmon5 BSP X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de LCD4 needs a slightly different GPIO configuration than the original LWMON5 variant. GPIO49 needs to be configured to a default output value of 0 (permanent voltage supply). Additionally lcd4 also needs to enable the LSB transmitter. Signed-off-by: Stefan Roese --- board/lwmon5/lwmon5.c | 3 +++ include/configs/lwmon5.h | 10 +++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 4e4a594..e9aa0b7 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -527,6 +527,9 @@ void spl_board_init(void) */ board_early_init_f(); + /* enable the LSB transmitter */ + gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); + /* * Clear resets */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 8f5eb95..96f3ba5 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -565,6 +565,7 @@ #define CONFIG_SYS_GPIO_PHY1_RST 12 #define CONFIG_SYS_GPIO_FLASH_WP 14 #define CONFIG_SYS_GPIO_PHY0_RST 22 +#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49 #define CONFIG_SYS_GPIO_DSPIC_READY 51 #define CONFIG_SYS_GPIO_CAN_ENABLE 53 #define CONFIG_SYS_GPIO_LSB_ENABLE 54 @@ -577,6 +578,13 @@ #define CONFIG_SYS_GPIO_SYSMON_STATUS 62 #define CONFIG_SYS_GPIO_WATCHDOG 63 +/* On LCD4, GPIO49 has to be configured to 0 instead of 1 */ +#ifdef CONFIG_LCD4_LWMON5 +#define GPIO49_VAL 0 +#else +#define GPIO49_VAL 1 +#endif + /* * PPC440 GPIO Configuration */ @@ -635,7 +643,7 @@ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \