From patchwork Mon Aug 5 10:43:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ramneek mehresh X-Patchwork-Id: 264629 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 1134B2C008A for ; Mon, 5 Aug 2013 20:59:01 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 39B5B4A021; Mon, 5 Aug 2013 12:58:59 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pn8hyBON2icp; Mon, 5 Aug 2013 12:58:59 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B487D4A019; Mon, 5 Aug 2013 12:58:57 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 93CBE4A019 for ; Mon, 5 Aug 2013 12:58:51 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id c+xpSL5co1hv for ; Mon, 5 Aug 2013 12:58:46 +0200 (CEST) X-Greylist: delayed 908 seconds by postgrey-1.27 at theia; Mon, 05 Aug 2013 12:58:39 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from db8outboundpool.messaging.microsoft.com (mail-db8lp0189.outbound.messaging.microsoft.com [213.199.154.189]) by theia.denx.de (Postfix) with ESMTPS id 857A64A018 for ; Mon, 5 Aug 2013 12:58:39 +0200 (CEST) Received: from mail206-db8-R.bigfish.com (10.174.8.227) by DB8EHSOBE042.bigfish.com (10.174.4.105) with Microsoft SMTP Server id 14.1.225.22; Mon, 5 Aug 2013 10:43:30 +0000 Received: from mail206-db8 (localhost [127.0.0.1]) by mail206-db8-R.bigfish.com (Postfix) with ESMTP id 60D9A2E008F for ; Mon, 5 Aug 2013 10:43:30 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dc1h1de2h1dfeh1dffh1e23h1155h) Received: from mail206-db8 (localhost.localdomain [127.0.0.1]) by mail206-db8 (MessageSwitch) id 1375699408532442_22456; Mon, 5 Aug 2013 10:43:28 +0000 (UTC) Received: from DB8EHSMHS017.bigfish.com (unknown [10.174.8.246]) by mail206-db8.bigfish.com (Postfix) with ESMTP id 73EA320046 for ; Mon, 5 Aug 2013 10:43:28 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS017.bigfish.com (10.174.4.27) with Microsoft SMTP Server (TLS) id 14.16.227.3; Mon, 5 Aug 2013 10:43:27 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.3.136.1; Mon, 5 Aug 2013 10:43:26 +0000 Received: from localhost.ap.freescale.net (B31383-04.ap.freescale.net [10.232.134.80]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r75AhLHv028718; Mon, 5 Aug 2013 03:43:24 -0700 From: Ramneek Mehresh To: Date: Mon, 5 Aug 2013 16:13:18 +0530 Message-ID: <1375699398-14812-1-git-send-email-ramneek.mehresh@freescale.com> X-Mailer: git-send-email 1.7.11.7 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: Ramneek Mehresh , Suresh Gupta Subject: [U-Boot] [PATCH 1/2]powerpc/usb: Workaround for erratum-A006918 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Erratum-A006918 prevents internal UTMI dual phy pll inside T4240 rev 1.0 from starting sometimes. Workaround involves restarting phy pll maximum seven times with 1ms delay in each loop Signed-off-by: Ramneek Mehresh Signed-off-by: Suresh Gupta --- Applies on git://git.denx.de/u-boot.git (branch master) arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 +++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 55 +++++++++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + include/fsl_usb.h | 7 ++++ 4 files changed, 67 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 5cd02cc..779b352 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -195,6 +195,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) puts("Work-around for Erratum DDR111 enabled\n"); puts("Work-around for Erratum DDR134 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006918 + if (IS_SVR_REV(svr, 1, 0)) + puts("Work-around for Erratum A006918 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 puts("Work-around for Erratum IFC-A002769 enabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 5aa09c1..6024768 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -35,6 +35,10 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SYS_FSL_ERRATUM_A006918 +bool has_fsl_erratum_a006918; +#endif + #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -211,6 +215,47 @@ static void corenet_tb_init(void) } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006918 +void fsl_erratum_a006918_workaround(void) +{ + unsigned int cnt = FSL_MAX_USBPLL_RETRY_COUNT; + struct ccsr_usb_phy *usb_phy = + (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; + + has_fsl_erratum_a006918 = true; + + do { + /* 1ms delay required for PLL to be stable */ + mdelay(1); + if ((in_be32(&usb_phy->port1.sts) & + CONFIG_SYS_FSL_USB_SYS_CLK_VALID) && + (in_be32(&usb_phy->port2.sts) & + CONFIG_SYS_FSL_USB_SYS_CLK_VALID)) { + has_fsl_erratum_a006918 = false; + break; + } else { + clrsetbits_be32(&usb_phy->pllprg[1], + CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN, + CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | + CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | + CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN | + CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV | + CONFIG_SYS_FSL_USB_PLLPRG2_MFI); + setbits_be32(&usb_phy->pllprg[1], + CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | + CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | + CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN | + CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV | + CONFIG_SYS_FSL_USB_PLLPRG2_MFI | + CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); + } + } while (--cnt); + + if (has_fsl_erratum_a006918) + printf("ERROR:fsl internal utmi phy init failed\n"); +} +#endif + void cpu_init_f (void) { extern void m8560_cpm_reset (void); @@ -628,6 +673,8 @@ skip_l2: #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) struct ccsr_usb_phy __iomem *usb_phy = (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; + setbits_be32(&usb_phy->pllprg[0], + CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV); setbits_be32(&usb_phy->pllprg[1], CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | @@ -645,6 +692,14 @@ skip_l2: CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); setbits_be32(&usb_phy->port2.pwrfltcfg, CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); + + /* Deal with USB Erratum USB-A006918 + * UTMI phy clk instability issue + */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A006918 + if (IS_SVR_REV(svr, 1, 0)) + fsl_erratum_a006918_workaround(); +#endif #endif #ifdef CONFIG_FMAN_ENET diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7ed93ac..f7926ef 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -542,6 +542,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A006918 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_PCI_VER_3_X diff --git a/include/fsl_usb.h b/include/fsl_usb.h index 88d6a1f..a3e681b 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -25,6 +25,8 @@ #ifndef _ASM_FSL_USB_H_ #define _ASM_FSL_USB_H_ +#include + #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE struct ccsr_usb_port_ctrl { u32 ctrl; @@ -68,6 +70,11 @@ struct ccsr_usb_phy { #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16) #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21) #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0) + +#ifdef CONFIG_SYS_FSL_ERRATUM_A006918 +extern bool has_fsl_erratum_a006918; +#define FSL_MAX_USBPLL_RETRY_COUNT 7 +#endif #else struct ccsr_usb_phy { u8 res0[0x18];