From patchwork Thu Jul 25 07:44:43 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ying.zhang@freescale.com X-Patchwork-Id: 261621 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 927B22C008C for ; Thu, 25 Jul 2013 18:42:44 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E06BF4A02C; Thu, 25 Jul 2013 10:41:56 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 54AnLRvYLYHS; Thu, 25 Jul 2013 10:41:56 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 762544A054; Thu, 25 Jul 2013 10:41:10 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9B6554A02A for ; Thu, 25 Jul 2013 10:41:03 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id r+gM59a25zOl for ; Thu, 25 Jul 2013 10:40:58 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from db9outboundpool.messaging.microsoft.com (mail-db9lp0252.outbound.messaging.microsoft.com [213.199.154.252]) by theia.denx.de (Postfix) with ESMTPS id 4AD394A01B for ; Thu, 25 Jul 2013 10:40:45 +0200 (CEST) Received: from mail219-db9-R.bigfish.com (10.174.16.247) by DB9EHSOBE041.bigfish.com (10.174.14.104) with Microsoft SMTP Server id 14.1.225.22; Thu, 25 Jul 2013 08:40:45 +0000 Received: from mail219-db9 (localhost [127.0.0.1]) by mail219-db9-R.bigfish.com (Postfix) with ESMTP id 3610A60116; Thu, 25 Jul 2013 08:40:45 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h1de097h8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h1354h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dfeh1dffh1e23h1155h) Received: from mail219-db9 (localhost.localdomain [127.0.0.1]) by mail219-db9 (MessageSwitch) id 1374741643146555_28119; Thu, 25 Jul 2013 08:40:43 +0000 (UTC) Received: from DB9EHSMHS030.bigfish.com (unknown [10.174.16.236]) by mail219-db9.bigfish.com (Postfix) with ESMTP id 1FCCF400043; Thu, 25 Jul 2013 08:40:43 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB9EHSMHS030.bigfish.com (10.174.14.40) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 25 Jul 2013 08:40:42 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.3.136.1; Thu, 25 Jul 2013 08:40:40 +0000 Received: from localhost.localdomain (tank.ap.freescale.net [10.193.20.104]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r6P8eSYL021821; Thu, 25 Jul 2013 01:40:39 -0700 From: To: Date: Thu, 25 Jul 2013 15:44:43 +0800 Message-ID: <1374738285-23184-5-git-send-email-ying.zhang@freescale.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1374738285-23184-1-git-send-email-ying.zhang@freescale.com> References: <1374738285-23184-1-git-send-email-ying.zhang@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: scottwood@freescale.com, afleming@gmail.com, X.Xie@freescale.com, Ying Zhang Subject: [U-Boot] [PATCH 5/7 v10] powerpc : p1022ds : enable p1022ds to start from eSPI with SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Ying Zhang Enable p1022ds to start from eSPI with SPL. Signed-off-by: Ying Zhang --- Change from v9: - No change. Change from v8: - No change. Change from v7: - No change. Change from v6: - No longer changes the header file included by the file. - "board/freescale/p1022ds/spl.c". Change from v5: - Split from "powerpc/p1022ds: boot from spi flash with SPL". - this patch enable P1022DS to start from eSPI with SPL. Change from v4: - No change. Change from v3: - No change. Change from v2: - No change. Change from v1: - Split from "boot from SD card/SPI flash with SPL". board/freescale/p1022ds/spl.c | 10 ++++++++++ include/configs/P1022DS.h | 36 +++++++++++++++++++++++++++++------- 2 files changed, 39 insertions(+), 7 deletions(-) diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c index cc3000a..1d52981 100644 --- a/board/freescale/p1022ds/spl.c +++ b/board/freescale/p1022ds/spl.c @@ -27,6 +27,7 @@ #include #include "../common/ngpixis.h" #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -53,6 +54,11 @@ void board_init_f(ulong bootflag) setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); +#ifdef CONFIG_SPL_SPI_BOOT + /* Enable the SPI */ + clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); +#endif + /* Read back the register to synchronize the write. */ in_be32(&gur->pmuxcr); @@ -66,6 +72,8 @@ void board_init_f(ulong bootflag) bus_clk / 16 / CONFIG_BAUDRATE); #ifdef CONFIG_SPL_MMC_BOOT puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI Flash boot...\n"); #endif /* copy code to RAM and jump to it - this should not return */ @@ -106,5 +114,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); #endif } diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 5a532f4..11c464e 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -48,11 +48,33 @@ #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_PAD_TO 0x18000 +#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_SPI_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif #endif #define CONFIG_NAND_FSL_ELBC @@ -318,7 +340,7 @@ * Config the L2 Cache as L2 SRAM */ #if defined(CONFIG_SPL_BUILD) -#if defined(CONFIG_SDCARD) +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_L2_SIZE (256 << 10) @@ -562,7 +584,7 @@ /* * Environment */ -#ifdef CONFIG_RAMBOOT_SPIFLASH +#ifdef CONFIG_SPIFLASH #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0