From patchwork Mon Jul 8 10:34:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mugunthan V N X-Patchwork-Id: 257518 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 92D8C2C007E for ; Mon, 8 Jul 2013 20:51:05 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4EC9B4A0F3; Mon, 8 Jul 2013 12:51:04 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bV9T2usBTAwq; Mon, 8 Jul 2013 12:51:04 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 56B394A0F4; Mon, 8 Jul 2013 12:50:20 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EE0794A092 for ; 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Mon, 8 Jul 2013 05:33:06 -0500 Received: from a0131834-linux.india.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dlelxv24.itg.ti.com (8.13.8/8.13.8) with ESMTP id r68AWx0u007959; Mon, 8 Jul 2013 05:33:05 -0500 From: Mugunthan V N To: Date: Mon, 8 Jul 2013 16:04:39 +0530 Message-ID: <1373279683-12421-4-git-send-email-mugunthanvnm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1373279683-12421-1-git-send-email-mugunthanvnm@ti.com> References: <1373279683-12421-1-git-send-email-mugunthanvnm@ti.com> MIME-Version: 1.0 X-Mailman-Approved-At: Mon, 08 Jul 2013 12:50:15 +0200 Cc: trini@ti.com, Mugunthan V N Subject: [U-Boot] [PATCH 3/7] ARM: DRA7xx: Lock DPLL_GMAC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Lokesh Vutla Locking DPLL_GMAC [mugunthanvnm@ti.com:Configure only if CPSW is selected] Signed-off-by: Lokesh Vutla Signed-off-by: Mugunthan V N --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 18 ++++++++++++++++++ arch/arm/cpu/armv7/omap5/hw_data.c | 11 +++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 + arch/arm/include/asm/omap_common.h | 2 ++ 4 files changed, 32 insertions(+) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index ef23127..e26d741 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -212,6 +212,18 @@ static const struct dpll_params *get_ddr_dpll_params return &dpll_data->ddr[sysclk_ind]; } +#ifdef CONFIG_DRIVER_TI_CPSW +static const struct dpll_params *get_gmac_dpll_params + (struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + + if (!dpll_data->gmac) + return NULL; + return &dpll_data->gmac[sysclk_ind]; +} +#endif + static void do_setup_dpll(u32 const base, const struct dpll_params *params, u8 lock, char *dpll) { @@ -414,6 +426,12 @@ static void setup_dplls(void) params = get_ddr_dpll_params(*dplls_data); do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy, params, DPLL_LOCK, "ddr"); + +#ifdef CONFIG_DRIVER_TI_CPSW + params = get_gmac_dpll_params(*dplls_data); + do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params, + DPLL_LOCK, "gmac"); +#endif } #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 56cf1f8..c909dcd 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -263,6 +263,16 @@ static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ }; +static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = { + {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */ + {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */ + {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + struct dplls omap5_dplls_es1 = { .mpu = mpu_dpll_params_800mhz, .core = core_dpll_params_2128mhz_ddr532, @@ -299,6 +309,7 @@ struct dplls dra7xx_dplls = { .iva = iva_dpll_params_2330mhz_dra7xx, .usb = usb_dpll_params_1920mhz, .ddr = ddr_dpll_params_2128mhz, + .gmac = gmac_dpll_params_2000mhz, }; struct pmic_data palmas = { diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index e839ff5..7793763 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -814,6 +814,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c, .cm_clkmode_dpll_dsp = 0x4a005234, .cm_shadow_freq_config1 = 0x4a005260, + .cm_clkmode_dpll_gmac = 0x4a0052a8, /* cm1.mpu */ .cm_mpu_mpu_clkctrl = 0x4a005320, diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 0dbe81b..8b4201b 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -89,6 +89,7 @@ struct prcm_regs { u32 cm_ssc_deltamstep_dpll_ddrphy; u32 cm_clkmode_dpll_dsp; u32 cm_shadow_freq_config1; + u32 cm_clkmode_dpll_gmac; u32 cm_mpu_mpu_clkctrl; /* cm1.dsp */ @@ -499,6 +500,7 @@ struct dplls { const struct dpll_params *iva; const struct dpll_params *usb; const struct dpll_params *ddr; + const struct dpll_params *gmac; }; struct pmic_data {