From patchwork Thu May 2 22:44:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 241114 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 7FDB62C00C9 for ; Fri, 3 May 2013 08:46:08 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 360754A3DF; Fri, 3 May 2013 00:46:06 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id SsObeRkfZuaK; Fri, 3 May 2013 00:46:06 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D418E4A385; Fri, 3 May 2013 00:45:17 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 72CF24A385 for ; Fri, 3 May 2013 00:45:15 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vZtIzqtOhFDB for ; Fri, 3 May 2013 00:45:10 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ye0-f173.google.com (mail-ye0-f173.google.com [209.85.213.173]) by theia.denx.de (Postfix) with ESMTPS id 598704A345 for ; Fri, 3 May 2013 00:44:55 +0200 (CEST) Received: by mail-ye0-f173.google.com with SMTP id l2so175018yen.32 for ; Thu, 02 May 2013 15:44:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=RHKZaJS8gsPwZ6wGCznyn9RkeMqRi7+rCaPfDSntl4o=; b=dA/BhsZ3eQq7RefcxrIIjERsGfegdZoIYb9asgnmj9PuGe2XIne54MejDsveD5NGRR PQSxz8MSey8suNAO9iofAi+0yiAd389veATh3ErjNSPZCL8XrwQc2fgtCxchTE/Ts4yD d2nbAK81XNtamSbfMOQRl7O5Si7YEnodzQz3k0T9hqbHgN5HqgOmY1BZwXu3nds5qGT8 Hq1KkmzZD6titFhVp5sNE8RC1NCXv2AC881w5+0YqUP4ckw6yu954DhPlVTGvVT1FVoE SylvcvV1wx5Lz1s3T7HdfAmMSdpoaeLv43h8D83jeqMJZ89JYqVLQGoPF3arMAAGe80S zGrA== X-Received: by 10.236.135.103 with SMTP id t67mr6793896yhi.54.1367534694714; Thu, 02 May 2013 15:44:54 -0700 (PDT) Received: from localhost.localdomain ([187.106.36.101]) by mx.google.com with ESMTPSA id n15sm16093242yhi.2.2013.05.02.15.44.52 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 02 May 2013 15:44:54 -0700 (PDT) From: Fabio Estevam To: sbabic@denx.de Date: Thu, 2 May 2013 19:44:21 -0300 Message-Id: <1367534661-13502-8-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1367534661-13502-1-git-send-email-festevam@gmail.com> References: <1367534661-13502-1-git-send-email-festevam@gmail.com> Cc: marex@denx.de, u-boot@lists.denx.de, otavio@ossystems.com.br, Fabio Estevam Subject: [U-Boot] [PATCH v3 7/7] mxs: spl_mem_init: Change EMI port priority X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Fabio Estevam FSL bootlets code set the PORT_PRIORITY_ORDER field of register HW_EMI_CTRL as 0x2, which means: PORT0231 = 0x02 Priority Order: AXI0, AHB2, AHB3, AHB1 Signed-off-by: Fabio Estevam --- Changes since v2: - None Changes since v1: - None arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index bf58058..5d881da 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -286,7 +286,7 @@ static void mx23_mem_init(void) early_delay(20000); /* Adjust EMI port priority. */ - clrsetbits_le32(0x80020000, 0x1f << 16, 0x8); + clrsetbits_le32(0x80020000, 0x1f << 16, 0x2); early_delay(20000); setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);