From patchwork Fri Apr 26 13:14:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 239868 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4629C2C00D6 for ; Fri, 26 Apr 2013 23:17:02 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DB6F94A10D; Fri, 26 Apr 2013 15:16:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lDpfxTmmPamY; Fri, 26 Apr 2013 15:16:50 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AC9F04A114; Fri, 26 Apr 2013 15:16:38 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AFB544A0ED for ; Fri, 26 Apr 2013 15:16:31 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IXJ60-tZewjJ for ; Fri, 26 Apr 2013 15:16:30 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ia0-f175.google.com (mail-ia0-f175.google.com [209.85.210.175]) by theia.denx.de (Postfix) with ESMTPS id 159EB4A0BF for ; Fri, 26 Apr 2013 15:16:20 +0200 (CEST) Received: by mail-ia0-f175.google.com with SMTP id i38so3687231iae.34 for ; Fri, 26 Apr 2013 06:16:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=h2w+XIr5POj/+8deja7tOHhuE3TyuYcWWlpzFFCe3Vc=; b=aCIiQRay84PC8D+WvklQAaF69k93Wly5vmkXzcOsvvIGnmQ/y5m18aW6r1KaDduYMB 3Jbqy2xMw9Vepp9X0b2ZRl68g33iZFjKKRSEEd/jGlOXDe1bani4zof+h+BhqQXBr4ua ciq0S+sfqgU/62HbgxCRV6v3xgbhU/y8PNc9oIg3umc3j4W0C49qvL8w1F2u8sOSitTV rFRbw+kRQIOwlSdaPGXXZhuhsNFE+muuRJCA5UOZYcufIsFY3FwRZ5+EJdDWOGCTk0No 2HbvFSIOWtLyGSxRxp6e1m9WUKVAPjas1tgaBBQJYiaypbzoLEtuhqZJyLik5NoAF0og 1I+Q== X-Received: by 10.50.134.10 with SMTP id pg10mr1880919igb.16.1366982178997; Fri, 26 Apr 2013 06:16:18 -0700 (PDT) Received: from slackpad.drs.calxeda.com (f053081241.adsl.alicedsl.de. [78.53.81.241]) by mx.google.com with ESMTPSA id b6sm3105602igv.5.2013.04.26.06.16.16 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 26 Apr 2013 06:16:18 -0700 (PDT) From: Andre Przywara To: trini@ti.com, albert.u.boot@aribaud.net Date: Fri, 26 Apr 2013 15:14:57 +0200 Message-Id: <1366982099-22360-5-git-send-email-andre.przywara@linaro.org> X-Mailer: git-send-email 1.7.12.1 In-Reply-To: <1366982099-22360-1-git-send-email-andre.przywara@linaro.org> References: <1366982099-22360-1-git-send-email-andre.przywara@linaro.org> X-Gm-Message-State: ALoCoQlwM5oN2yJvNLhrVzarrTqm9dITM5DsjqyaO+l4+Gek+O1S4olLMBQWQ26Ja+mw9E+mjjA/ Cc: cdall@cs.columbia.edu, geoff.levand@linaro.org, marc.zyngier@arm.com, agraf@suse.de, u-boot@lists.denx.de, kvmarm@lists.cs.columbia.edu Subject: [U-Boot] [RFC PATCH 4/6] ARM: add SMP support for non-secure switch X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Currently the non-secure switch is only done for the boot processor. To later allow full SMP support, we have to switch all secondary cores into non-secure state also. So we add an entry point for secondary CPUs coming out of low-power state and make sure we put them into WFI again after having switched to non-secure state. For this we acknowledge and EOI the wake-up IPI, then go into WFI. Once being kicked out of it later, we sanity check that the start address has actually been changed (since another attempt to switch to non-secure would block the core) and jump to the new address. The actual CPU kick is done by sending an inter-processor interrupt via the GIC to all CPU interfaces except the requesting processor. The secondary cores will then setup their respective GIC CPU interface. The address secondary cores jump to is board specific, we provide the value here for the Versatile Express board. Signed-off-by: Andre Przywara --- arch/arm/cpu/armv7/start.S | 27 ++++++++++++++++++++++++++- arch/arm/lib/virt-v7.c | 10 +++++++++- include/configs/vexpress_ca15_tc2.h | 1 + 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 401b0eb..2b47881 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -563,8 +563,19 @@ fiq: #endif /* CONFIG_SPL_BUILD */ /* Routine to initialize GIC CPU interface and switch to nonsecure state. + * Will be executed directly by secondary CPUs after coming out of + * WFI, or can be called directly by C code for CPU 0. + * Those two paths mandate to not use any stack and to only use registers + * r0-r3 to comply with both the C ABI and the requirement of SMP startup + * code. */ .globl _nonsec_gic_switch +.globl _smp_pen +_smp_pen: + mrs r0, cpsr + orr r0, r0, #0xc0 + msr cpsr, r0 @ disable interrupts + mov lr, #0 @ clear LR to mark secondary _nonsec_gic_switch: mrc p15, 4, r2, c15, c0, 0 @ r2 = PERIPHBASE add r3, r2, #0x1000 @ GIC dist i/f offset @@ -605,4 +616,18 @@ _nonsec_gic_switch: add r2, r2, #0x1000 @ GIC dist i/f offset str r1, [r2] @ allow private interrupts - mov pc, lr + cmp lr, #0 + movne pc, lr @ CPU 0 to return + @ all others: go to sleep +_ack_int: + ldr r1, [r3, #0x0c] @ read GICD acknowledge + str r1, [r3, #0x10] @ write GICD EOI + + adr r1, _smp_pen +waitloop: + wfi + ldr r0, =CONFIG_SYSFLAGS_ADDR @ load start address + ldr r0, [r0] + cmp r0, r1 @ make sure we dont execute this code + beq waitloop @ again (due to a spurious wakeup) + mov pc, r0 diff --git a/arch/arm/lib/virt-v7.c b/arch/arm/lib/virt-v7.c index 416ca29..5ca093a 100644 --- a/arch/arm/lib/virt-v7.c +++ b/arch/arm/lib/virt-v7.c @@ -29,6 +29,7 @@ /* the assembly routine doing the actual work in start.S */ void _nonsec_gic_switch(void); +void _smp_pen(void); #define GICD_CTLR 0x000 #define GICD_TYPER 0x004 @@ -51,6 +52,7 @@ int armv7_switch_nonsec(void) unsigned int reg; volatile unsigned int *gicdptr; unsigned itlinesnr, i; + unsigned int *sysflags; /* check whether the CPU supports the security extensions */ asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg)); @@ -109,7 +111,13 @@ int armv7_switch_nonsec(void) for (i = 0; i <= itlinesnr; i++) gicdptr[GICD_IGROUPR0 / 4 + i] = (unsigned)-1; - /* call the non-sec switching code on this CPU */ + /* now kick all CPUs (expect this one) by writing to GICD_SIGR */ + sysflags = (void *)CONFIG_SYSFLAGS_ADDR; + sysflags[1] = (unsigned)-1; + sysflags[0] = (uintptr_t)_smp_pen; + gicdptr[GICD_SGIR / 4] = 1U << 24; + + /* call the non-sec switching code on this CPU also */ _nonsec_gic_switch(); return 0; diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h index 9e230ad..210a27c 100644 --- a/include/configs/vexpress_ca15_tc2.h +++ b/include/configs/vexpress_ca15_tc2.h @@ -32,5 +32,6 @@ #define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.vexpress_ca15x2_tc2" #define CONFIG_SYS_CLK_FREQ 24000000 +#define CONFIG_SYSFLAGS_ADDR 0x1c010030 #endif