From patchwork Tue Apr 9 23:06:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 235260 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0EC872C00BB for ; Wed, 10 Apr 2013 09:07:04 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 044B04A01E; Wed, 10 Apr 2013 01:07:00 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 82yhTwqS5PUZ; Wed, 10 Apr 2013 01:06:59 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C36B34A021; Wed, 10 Apr 2013 01:06:55 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9DD644A021 for ; Wed, 10 Apr 2013 01:06:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Dka-tA3W8eyd for ; Wed, 10 Apr 2013 01:06:48 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-gg0-f172.google.com (mail-gg0-f172.google.com [209.85.161.172]) by theia.denx.de (Postfix) with ESMTPS id 076D44A01E for ; Wed, 10 Apr 2013 01:06:43 +0200 (CEST) Received: by mail-gg0-f172.google.com with SMTP id f4so1174959ggn.3 for ; Tue, 09 Apr 2013 16:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=YelcuN1sM73pNkNJSfwtsF06hqM8tUl0XdOhHZAVers=; b=Wf9q4kl026muERTeFNkAIZH3Qx6nmNP3rFfBU9W3SQf2p4z6ZVkzXoKYCKw+n1unkY cUmJ5oopwdLseZdus/zxrIMScJxH+1sibkjT5nak3bkkvPvl026D5c5KRnBSAg7u8gNN qnut/ZjK4Bz8bKkznPzH+exSwA/VZlpikpLgT+i5mrLa2Co7HQUiIeIdjYtwDNpwxKqC jDT1iTjDcXgj1Uq8DltTeK8IOoDB9XuRAU1Y0XmPMca9SPZbr2ohl1UXbTDyRR8/bPAY dWGFkkjdws/eDsIXSUX7zG3FkaHi1xZL1Km8hTgFNwmKVn609/Dafl3+2XRFCM2kvFZ/ i7jw== X-Received: by 10.236.222.130 with SMTP id t2mr16679678yhp.165.1365548798097; Tue, 09 Apr 2013 16:06:38 -0700 (PDT) Received: from localhost.localdomain ([187.64.220.204]) by mx.google.com with ESMTPS id w69sm46094119yhe.4.2013.04.09.16.06.35 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 09 Apr 2013 16:06:37 -0700 (PDT) From: Fabio Estevam To: sbabic@denx.de Date: Tue, 9 Apr 2013 20:06:25 -0300 Message-Id: <1365548785-28684-1-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.7.9.5 Cc: Fabio Estevam , u-boot@lists.denx.de, dirk.behme@de.bosch.com Subject: [U-Boot] [PATCH v2] spi: mxc_spi: Set master mode for all channels X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Fabio Estevam The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam --- Changes since v1: - Introduce MXC_CSPICTRL_MODE_MASK definition - Remove additional read of reg_ctrl arch/arm/include/asm/arch-mx5/imx-regs.h | 1 + arch/arm/include/asm/arch-mx6/imx-regs.h | 1 + drivers/spi/mxc_spi.c | 17 +++++++++-------- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 249d15a..a71cc13 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -230,6 +230,7 @@ #define MXC_CSPICTRL_EN (1 << 0) #define MXC_CSPICTRL_MODE (1 << 1) #define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_MODE_MASK (0xf << 4) #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index eaa7439..d79ab2f 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -346,6 +346,7 @@ struct cspi_regs { #define MXC_CSPICTRL_EN (1 << 0) #define MXC_CSPICTRL_MODE (1 << 1) #define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_MODE_MASK (0xf << 4) #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 4c19e0b..20419e6 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -137,11 +137,15 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, return -1; } - /* Reset spi */ - reg_write(®s->ctrl, 0); - reg_write(®s->ctrl, MXC_CSPICTRL_EN); - - reg_ctrl = reg_read(®s->ctrl); + /* + * Reset SPI and set all CSs to master mode, if toggling + * between slave and master mode we might see a glitch + * on the clock line + */ + reg_ctrl = MXC_CSPICTRL_MODE_MASK; + reg_write(®s->ctrl, reg_ctrl); + reg_ctrl |= MXC_CSPICTRL_EN; + reg_write(®s->ctrl, reg_ctrl); /* * The following computation is taken directly from Freescale's code. @@ -174,9 +178,6 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | MXC_CSPICTRL_POSTDIV(post_div); - /* always set to master mode */ - reg_ctrl |= 1 << (cs + 4); - /* We need to disable SPI before changing registers */ reg_ctrl &= ~MXC_CSPICTRL_EN;