From patchwork Fri Mar 29 20:38:10 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Warren X-Patchwork-Id: 232492 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id C610D2C00BC for ; Sat, 30 Mar 2013 08:09:13 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9CF034A023; Fri, 29 Mar 2013 22:09:10 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7CjuobH2belB; Fri, 29 Mar 2013 22:09:10 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E08444A025; Fri, 29 Mar 2013 22:09:07 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AEEF24A025 for ; Fri, 29 Mar 2013 22:09:04 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KOfyIsr6X-4U for ; Fri, 29 Mar 2013 22:09:00 +0100 (CET) X-Greylist: delayed 1820 seconds by postgrey-1.27 at theia; Fri, 29 Mar 2013 22:08:58 CET X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-gg0-f177.google.com (mail-gg0-f177.google.com [209.85.161.177]) by theia.denx.de (Postfix) with ESMTPS id 1EB1F4A023 for ; Fri, 29 Mar 2013 22:08:58 +0100 (CET) Received: by mail-gg0-f177.google.com with SMTP id q1so75108gge.8 for ; Fri, 29 Mar 2013 14:08:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-nvconfidentiality; bh=WkqK9IFh+QEKS8pkNyQfu39RCO7zgLcARMTQVO9E4Fk=; b=DZzxv+zUtOlJsK9SCNMOXn0Y+JUj3zjbopenP+tvB6RfhYnu2lu0vr3KPgp2bFZu9u lEPRJM43MLsmnnHXKa03c0EAnG1gvr/rbLm1t/KRXn5AAnsXGcWP5xICgVRNSuNlc3Qi A57dEoSKvmyjYPDoQV4JM/AowJFlxSaI/uT5qm4oXU7/YmGmVIdOP5KLICJANtFR6scX ys4mxdIuXnBUT1/XcubkHeJxdxdo5w7wdYwO29FsX5hcGIx2swVlahW2a/ORBo/OsPqD Z12qFIcRfLPmB9ySweK4mZUBbyOGrutAnqHiCUiv07OZxzfjkpjcjZ1gHI/9AauaGk3w OvmQ== X-Received: by 10.236.135.231 with SMTP id u67mr1390809yhi.135.1364589513605; Fri, 29 Mar 2013 13:38:33 -0700 (PDT) Received: from tom-ubuntu64.nvidia.com (ip68-230-103-25.ph.ph.cox.net. [68.230.103.25]) by mx.google.com with ESMTPS id o31sm3374830yhh.21.2013.03.29.13.38.30 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 29 Mar 2013 13:38:32 -0700 (PDT) From: Tom Warren To: u-boot@lists.denx.de Date: Fri, 29 Mar 2013 13:38:10 -0700 Message-Id: <1364589490-2759-1-git-send-email-twarren@nvidia.com> X-Mailer: git-send-email 1.8.1.5 X-NVConfidentiality: public Cc: swarren@nvidia.com, Tom Warren , twarren.nvidia@gmail.com Subject: [U-Boot] [PATCH] Tegra: Configure L2 cache control reg properly. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Without this change, kernel fails at calling function cache_clean_flush during kernel early boot. Aprocryphally, intended for T114 only, so I check for a T114 SoC. Works (i.e. dalmore 3.8 kernel now starts printing to console). Signed-off-by: Tom Warren --- arch/arm/cpu/tegra-common/Makefile | 2 +- arch/arm/cpu/tegra-common/ap.c | 9 ++----- arch/arm/cpu/tegra-common/cache.c | 48 ++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-tegra/ap.h | 1 + 4 files changed, 52 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/tegra-common/cache.c diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile index 8e95c7e..4e0301c 100644 --- a/arch/arm/cpu/tegra-common/Makefile +++ b/arch/arm/cpu/tegra-common/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libcputegra-common.o SOBJS += lowlevel_init.o -COBJS-y += ap.o board.o sys_info.o timer.o clock.o +COBJS-y += ap.o board.o sys_info.o timer.o clock.o cache.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index 3f30805..a739fe2 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -139,11 +139,6 @@ void s_init(void) enable_scu(); - /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #0x41\n" - "mcr p15, 0, r0, c1, c0, 1\n"); - - /* FIXME: should have SoC's L2 disabled too? */ + /* init the cache */ + config_cache(); } diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c new file mode 100644 index 0000000..48e9319 --- /dev/null +++ b/arch/arm/cpu/tegra-common/cache.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Tegra cache routines */ + +#include +#include +#include +#include + +void config_cache(void) +{ + struct apb_misc_gp_ctlr *gp = + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; + u32 reg = 0; + + /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #0x41\n" + "mcr p15, 0, r0, c1, c0, 1\n"); + + /* Currently, only T114 needs this L2 cache change to boot Linux */ + reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK); + if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT)) + return; + /* + * Systems with an architectural L2 cache must not use the PL310. + * Config L2CTLR here for a data RAM latency of 3 cycles. + */ + asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); + reg &= ~7; + reg |= 2; + asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); +} diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index 73dfd39..5999f55 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -64,3 +64,4 @@ extern void _start(void); * @return SOC type - see TEGRA_SOC... */ int tegra_get_chip_type(void); +void config_cache(void);