From patchwork Thu Mar 28 14:32:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Saraswat X-Patchwork-Id: 232043 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 1EC202C009C for ; Fri, 29 Mar 2013 01:13:52 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A33474A09D; Thu, 28 Mar 2013 15:13:40 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZzQkt8l6fzL1; Thu, 28 Mar 2013 15:13:40 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3A43D4A02A; Thu, 28 Mar 2013 15:13:12 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 654C24A03B for ; Thu, 28 Mar 2013 15:13:04 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id o4T7nT7OYaHC for ; Thu, 28 Mar 2013 15:13:03 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) by theia.denx.de (Postfix) with ESMTP id D55514A029 for ; Thu, 28 Mar 2013 15:12:46 +0100 (CET) Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MKD0020GJH3KY70@mailout1.samsung.com> for u-boot@lists.denx.de; Thu, 28 Mar 2013 23:12:46 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.124]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 15.25.20872.DDF44515; Thu, 28 Mar 2013 23:12:46 +0900 (KST) X-AuditID: cbfee68d-b7f786d000005188-39-51544fdda38b Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 61.B8.13494.DDF44515; Thu, 28 Mar 2013 23:12:45 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MKD00MY2JGUVB00@mmp2.samsung.com>; Thu, 28 Mar 2013 23:12:45 +0900 (KST) From: Akshay Saraswat To: u-boot@lists.denx.de, mk7.kang@samsung.com Date: Thu, 28 Mar 2013 10:32:21 -0400 Message-id: <1364481144-17495-8-git-send-email-akshay.s@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1364481144-17495-1-git-send-email-akshay.s@samsung.com> References: <1364481144-17495-1-git-send-email-akshay.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrGLMWRmVeSWpSXmKPExsWyRsSkRveef0igweYvLBYdR1oYLVYd3sBu MfXBOUaLb1u2MVq83dvJ7sDqMbvhIovHzll32T3O3tnB6NG3ZRVjAEsUl01Kak5mWWqRvl0C V8aCqwvZCu7qV/Te+cDWwLhNrYuRk0NCwERiVlczE4QtJnHh3no2EFtIYCmjxJtDsjA1txfO Zu5i5AKKT2eU+HXkBhuE08sk8X5yPytIFZuAjsT2Jd/ZQWwRAT2JeZPegU1iFnCU6LrzhxHE FhbwkXjT+5EZxGYRUJW4eOQmWA2vgItE0/Zp7BDb5CQ+7HkEZHNwcAq4SvxdIwpxkIvE4v0t zBAl7ewSN98YQYwRkPg2+RALSLmEgKzEpgNQJZISB1fcYJnAKLyAkWEVo2hqQXJBcVJ6kaFe cWJucWleul5yfu4mRmAYn/73rHcH4+0D1ocYk4HGTWSWEk3OB8ZBXkm8obGZkYWpiamxkbml GWnCSuK8ai3WgUIC6YklqdmpqQWpRfFFpTmpxYcYmTg4pRoYDwnmTqn5w79x9d+22TH3I6YZ c0yYos3l4+Dn0fH9RpWP2u4v30y8KnUVpN682fzzoR/zldpSOaNj+04bsgY73F1c1uiQcOWo YIq76yuGl2/PbjY+WHGqd827ZK7IBwz9cbmh/zhVD+QlBDzxlQ2YxPxu6YzJMz7tvGr4lLPX TJqDoergdv+TSizFGYmGWsxFxYkAubVmoHkCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKIsWRmVeSWpSXmKPExsVy+t9jQd27/iGBBk+OWVh0HGlhtFh1eAO7 xdQH5xgtvm3Zxmjxdm8nuwOrx+yGiyweO2fdZfc4e2cHo0ffllWMASxRDYw2GamJKalFCql5 yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5qbZKLj4Bum6ZOUCblRTKEnNKgUIBicXFSvp2 mCaEhrjpWsA0Ruj6hgTB9RgZoIGENYwZC64uZCu4q1/Re+cDWwPjNrUuRk4OCQETidsLZzND 2GISF+6tZ+ti5OIQEpjOKPHryA0op5dJ4v3kflaQKjYBHYntS76zg9giAnoS8ya9YwOxmQUc Jbru/GEEsYUFfCTe9H4Em8oioCpx8chNsBpeAReJpu3T2CG2yUl82PMIyObg4BRwlfi7RhQk LARUsnh/C/MERt4FjAyrGEVTC5ILipPSc430ihNzi0vz0vWS83M3MYIj5Zn0DsZVDRaHGAU4 GJV4eCsEggOFWBPLiitzDzFKcDArifBOlgkJFOJNSaysSi3Kjy8qzUktPsSYDHTURGYp0eR8 YBTnlcQbGpuYmxqbWppYmJhZkiasJM57sNU6UEggPbEkNTs1tSC1CGYLEwenVAPjTE6tbb6M erd3ri2q+pF09fWSSqdXi8/IhG3mENbiC7P//eCKA6tCwZdnQSmJvnaL5c10ap9cb0zt3FM6 Z7qOVVpGmERlmtsDQ62tiUccOlQC/nuL63gHM+h9UYqasDNkdW3bWU8mc7GytusmTAXOGQsX 9sYzyLU8V3j8e1t9zIMH5hMZVimxFGckGmoxFxUnAgBCRyT12AIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: prashanth.g@samsung.com Subject: [U-Boot] [PATCH 08/11 v3] Exynos: clock: Add generic api to get the clk freq X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Padmavathi Venna Add generic api to get the frequency of the required peripherial. This API gets the source clock frequency and returns the required frequency by dividing with first and second dividers based on the requirement. Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna Signed-off-by: Akshay Saraswat Acked-by: Simon Glass --- Changes since v2: - Fixed typo peripherial to peripheral. - Made exynos5_get_periph_rate static. - Added an empty line. - Replaced "enum periph_id" with "int" in function arguments. - Removed "#include " from clk.h. - Added "Acked-by: Simon Glass". Changes since v1: - Fixed few nits. arch/arm/cpu/armv7/exynos/clock.c | 144 +++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 15 ++++ 2 files changed, 159 insertions(+) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 956427c..5860c8f 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -27,6 +27,49 @@ #include #include +/* * + * This structure is to store the src bit, div bit and prediv bit + * positions of the peripheral clocks of the src and div registers + */ +struct clk_bit_info { + int8_t src_bit; + int8_t div_bit; + int8_t prediv_bit; +}; + +/* src_bit div_bit prediv_bit */ +static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { + {0, 0, -1}, + {4, 4, -1}, + {8, 8, -1}, + {12, 12, -1}, + {0, 0, 8}, + {4, 16, 24}, + {8, 0, 8}, + {12, 16, 24}, + {-1, -1, -1}, + {16, 0, 8}, + {20, 16, 24}, + {24, 0, 8}, + {0, 0, 4}, + {4, 12, 16}, + {-1, -1, -1}, + {-1, -1, -1}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, +}; + /* Epll Clock division values to achive different frequency output */ static struct set_epll_con_val exynos5_epll_div[] = { { 192000000, 0, 48, 3, 1, 0 }, @@ -201,6 +244,107 @@ static unsigned long exynos5_get_pll_clk(int pllreg) return fout; } +static unsigned long exynos5_get_periph_rate(int peripheral) +{ + struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; + unsigned long sclk, sub_clk; + unsigned int src, div, sub_div; + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + src = readl(&clk->src_peric0); + div = readl(&clk->div_peric0); + break; + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + case PERIPH_ID_PWM4: + src = readl(&clk->src_peric0); + div = readl(&clk->div_peric3); + break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + src = readl(&clk->src_peric1); + div = readl(&clk->div_peric1); + break; + case PERIPH_ID_SPI2: + src = readl(&clk->src_peric1); + div = readl(&clk->div_peric2); + break; + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + src = readl(&clk->sclk_src_isp); + div = readl(&clk->sclk_div_isp); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + src = readl(&clk->src_fsys); + div = readl(&clk->div_fsys1); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + sclk = exynos5_get_pll_clk(MPLL); + sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit) + & 0x7) + 1; + div = ((readl(&clk->div_top0) >> bit_info->prediv_bit) + & 0x7) + 1; + return (sclk / sub_div) / div; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + }; + + src = (src >> bit_info->src_bit) & 0xf; + + switch (src) { + case EXYNOS_SRC_MPLL: + sclk = exynos5_get_pll_clk(MPLL); + break; + case EXYNOS_SRC_EPLL: + sclk = exynos5_get_pll_clk(EPLL); + break; + case EXYNOS_SRC_VPLL: + sclk = exynos5_get_pll_clk(VPLL); + break; + default: + return 0; + } + + /* Ratio clock division for this peripheral */ + sub_div = (div >> bit_info->div_bit) & 0xf; + sub_clk = sclk / (sub_div + 1); + + /* Pre-ratio clock division for SDMMC0 and 2 */ + if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) { + div = (div >> bit_info->prediv_bit) & 0xff; + return sub_clk / (div + 1); + } + + return sub_clk; +} + +unsigned long clock_get_periph_rate(int peripheral) +{ + if (cpu_is_exynos5()) + return exynos5_get_periph_rate(peripheral); + else + return 0; +} + /* exynos4: return ARM clock frequency */ static unsigned long exynos4_get_arm_clk(void) { diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 1935b0b..73f8063 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -29,6 +29,12 @@ #define VPLL 4 #define BPLL 5 +enum pll_src_bit { + EXYNOS_SRC_MPLL = 6, + EXYNOS_SRC_EPLL, + EXYNOS_SRC_VPLL, +}; + unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_i2c_clk(void); @@ -44,4 +50,13 @@ int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq); int set_epll_clk(unsigned long rate); int set_spi_clk(int periph_id, unsigned int rate); +/** + * get the clk frequency of the required peripheral + * + * @param peripheral Peripheral id + * + * @return frequency of the peripheral clk + */ +unsigned long clock_get_periph_rate(int peripheral); + #endif